Lines Matching refs:gr5
63 setlos #32,gr5 ; cacheline size
96 ldi @(gr4,#0),gr5
97 ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
98 sti gr5,@(gr4,#0)
102 sethi.p %hi(__region_CS1_M),gr5
103 setlo %lo(__region_CS1_M),gr5
107 sti gr5,@(gr10,#1*0x08+0x100)
111 sethi.p %hi(__region_CS2_M),gr5
112 setlo %lo(__region_CS2_M),gr5
116 sti gr5,@(gr10,#2*0x08+0x100)
120 sethi.p %hi(__region_CS3_M),gr5
121 setlo %lo(__region_CS3_M),gr5
125 sti gr5,@(gr10,#3*0x08+0x100)
129 sethi.p %hi(__region_CS4_M),gr5
130 setlo %lo(__region_CS4_M),gr5
134 sti gr5,@(gr10,#4*0x08+0x100)
138 sethi.p %hi(__region_CS5_M),gr5
139 setlo %lo(__region_CS5_M),gr5
143 sti gr5,@(gr10,#5*0x08+0x100)
147 sethi.p %hi(__region_CS6_M),gr5
148 setlo %lo(__region_CS6_M),gr5
152 sti gr5,@(gr10,#6*0x08+0x100)
156 sethi.p %hi(__region_CS7_M),gr5
157 setlo %lo(__region_CS7_M),gr5
161 sti gr5,@(gr10,#7*0x08+0x100)
246 sethi.p %hi(__region_IO),gr5
247 setlo %lo(__region_IO),gr5
248 ori gr5,#xAMPRx_SS_512Mb|xAMPRx_S_KERNEL|xAMPRx_C|xAMPRx_V,gr5
250 movgs gr5,dampr7 ; General I/O tile
281 movgs gr5,dampr6
285 movgs gr5,dampr5
288 movgs gr5,dampr4
291 movgs gr5,dampr3
294 movgs gr5,dampr2
297 movgs gr5,dampr1
306 ori gr5,#xAMPRx_S_KERNEL,gr5
310 movgs gr5,dampr0