Lines Matching refs:gr5
64 setlos #32,gr5 ; cacheline size
89 ldi @(gr4,#0),gr5
90 ori gr5,#0xff,gr5 ; make sure all chip-selects are enabled
91 sti gr5,@(gr4,#0)
95 sethi.p %hi(__region_CS1_M),gr5
96 setlo %lo(__region_CS1_M),gr5
100 sti gr5,@(gr10,#1*0x08+0x100)
104 sethi.p %hi(__region_CS2_M),gr5
105 setlo %lo(__region_CS2_M),gr5
109 sti gr5,@(gr10,#2*0x08+0x100)
113 sethi.p %hi(__region_CS3_M),gr5
114 setlo %lo(__region_CS3_M),gr5
118 sti gr5,@(gr10,#3*0x08+0x100)
122 sethi.p %hi(__region_CS4_M),gr5
123 setlo %lo(__region_CS4_M),gr5
127 sti gr5,@(gr10,#4*0x08+0x100)
131 sethi.p %hi(__region_CS5_M),gr5
132 setlo %lo(__region_CS5_M),gr5
136 sti gr5,@(gr10,#5*0x08+0x100)
140 sethi.p %hi(__region_CS6_M),gr5
141 setlo %lo(__region_CS6_M),gr5
145 sti gr5,@(gr10,#6*0x08+0x100)
149 sethi.p %hi(__region_CS7_M),gr5
150 setlo %lo(__region_CS7_M),gr5
154 sti gr5,@(gr10,#7*0x08+0x100)
244 sethi.p %hi(__region_IO),gr5
245 setlo %lo(__region_IO),gr5
247 or gr4,gr5,gr4
248 movgs gr5,damlr11 ; General I/O tile
270 and gr5,gr11,gr5
272 or gr5,gr11,gr5
284 sethi.p %hi(PAGE_SIZE),gr5
285 setlo %lo(PAGE_SIZE),gr5
289 add gr4,gr5,gr4
291 add gr4,gr5,gr4
293 add gr4,gr5,gr4
295 add gr4,gr5,gr4
297 add gr4,gr5,gr4
299 add gr4,gr5,gr4
301 add gr4,gr5,gr4
303 add gr4,gr5,gr4
333 sethi.p %hi(__page_offset),gr5
334 setlo %lo(__page_offset),gr5
335 sub gr4,gr5,gr4
337 setlos #xAMPRx_L|xAMPRx_M|xAMPRx_SS_16Kb|xAMPRx_S|xAMPRx_C|xAMPRx_V,gr5
338 or gr4,gr5,gr4
360 sethi.p %hi(HSR0_ETMI),gr5
361 setlo %lo(HSR0_ETMI),gr5
362 or gr4,gr5,gr4