Lines Matching refs:reg
15 #define REG_RD( scope, inst, reg ) \
16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
21 #define REG_WR( scope, inst, reg, val ) \
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #define REG_RD_VECT( scope, inst, reg, index ) \
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
34 #define REG_WR_VECT( scope, inst, reg, index, val ) \
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
41 #define REG_RD_INT( scope, inst, reg ) \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #define REG_WR_INT( scope, inst, reg, val ) \
47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
53 (index) * STRIDE_##scope##_##reg )
57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
59 (index) * STRIDE_##scope##_##reg, (val) )
72 #define REG_ADDR( scope, inst, reg ) \
73 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #define REG_ADDR_VECT( scope, inst, reg, index ) \
78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
79 (index) * STRIDE_##scope##_##reg )