Lines Matching refs:ddr2
25 ;; Refer to ddr2 MDS for initialization sequence
33 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
34 move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
43 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
44 move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
45 REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
47 move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
56 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
74 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
79 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
84 move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0