Lines Matching defs:R0
33 R0 = IWR_ENABLE(0);
57 R3 = R0;
58 R0 = IWR_DISABLE_ALL;
81 P3 = R0;
85 R0 = IWR_ENABLE(0);
95 R0.L = 0xF;
96 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
101 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
102 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
125 R0 = P3;
132 R0 = W[P0](z);
133 BITSET (R0, 3);
134 W[P0] = R0.L; /* Turn CCLK OFF */
140 R0 = IWR_ENABLE(0);
257 [P0] = R0;
267 R0 = W[P0] (Z);
268 CC = BITTST(R0,5);
279 R2 = R0;
547 R0.H = 0xDEAD; /* Hibernate Magic */
548 R0.L = 0xBEEF;
549 [P0++] = R0; /* Store Hibernate Magic */
550 R0.H = .Lpm_resume_here;
551 R0.L = .Lpm_resume_here;
552 [P0++] = R0; /* Save Return Address */
556 R0 = R2;