Lines Matching refs:BFIN_IRQ
41 #define BFIN_IRQ(x) ((x) + 7)
43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44 #define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
45 #define IRQ_EPPI0_ERROR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
46 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
47 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
48 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
49 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
50 #define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
51 #define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
52 #define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
53 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
54 #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
55 #define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
56 #define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
57 #define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
58 #define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
59 #define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
60 #define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
61 #define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
62 #define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
63 #define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
64 #define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
65 #define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
66 #define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
67 #define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
68 #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
69 #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
70 #define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
71 #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
72 #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
73 #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
74 #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
75 #define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
76 #define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
77 #define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
78 #define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
79 #define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
80 #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
81 #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
82 #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
83 #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
84 #define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
85 #define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
86 #define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
87 #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
88 #define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
89 #define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
90 #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
91 #define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
92 #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
93 #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
94 #define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
95 #define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
96 #define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
97 #define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
98 #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
99 #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
100 #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
101 #define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
102 #define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
103 #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
104 #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
105 #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
106 #define IRQ_NFC_ERROR BFIN_IRQ(60) /* NFC Error Interrupt */
107 #define IRQ_ATAPI_ERROR BFIN_IRQ(61) /* ATAPI Error Interrupt */
108 #define IRQ_CAN1_ERROR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
109 #define IRQ_HS_DMA_ERROR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
110 #define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
111 #define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
112 #define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
113 #define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
114 #define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
115 #define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
116 #define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
117 #define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
118 #define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
119 #define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
120 #define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
121 #define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
122 #define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
123 #define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
124 #define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
125 #define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
126 #define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
127 #define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
128 #define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
129 #define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
130 #define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
131 #define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
132 #define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
133 #define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
134 #define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */