Lines Matching refs:x8
1518 #define SPORT0_ERR 0x8 /* SPORT0 Error */
1550 #define DMA20 0x8 /* DMA Channel 20 */
1588 #define DMA22 0x8 /* DMA Channel 22 */
1774 #define CORE_ERROR 0x8 /* Core error */
1784 #define SRREQ 0x8 /* Self-refresh request */
1793 #define B3WCENABLE 0x8 /* Bank 3 write count enable */
1820 #define CB3WCOUNT 0x8 /* Clear write count 3 */
1846 #define Px3 0x8 /* GPIO 3 */
1885 #define IB3 0x8 /* Interrupt Bit 3 */
1903 #define PERIOD_CNT 0x8 /* Period Count */
1917 #define TIMEN3 0x8 /* Timer 3 Enable */
1928 #define TIMDIS3 0x8 /* Timer 3 Disable */
1939 #define TIMIL3 0x8 /* Timer 3 Interrupt */
1979 #define SECURE3 0x8 /* SECURE 3 */
1985 #define AFVALID 0x8 /* Authentication Firmware Valid */
2001 #define LTERR_UNDR 0x8 /* Line Track Underflow */
2079 #define GM 0x8 /* Get More Data */
2087 #define FLS3 0x8 /* Slave Select Enable 3 */
2097 #define TXS 0x8 /* TDBR Data Buffer Status */
2135 #define NAK 0x8 /* Not Acknowledge */
2151 #define FAST 0x8 /* Fast Mode */
2167 #define DNAK 0x8 /* Data Not Acknowledged */
2179 #define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
2191 #define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
2202 #define SOVF 0x8 /* Slave Overflow */
2227 #define PEN 0x8 /* Parity Enable */
2237 #define RFRT 0x8 /* Receive FIFO RTS Threshold */
2248 #define FE 0x8 /* Framing Error */
2265 #define EDSSI 0x8 /* Enable Modem Status Interrupt */
2275 #define RPOLC 0x8 /* IrDA RX Polarity Change */