Lines Matching refs:x8
499 #define IMG_FORM 0x8 /* Image Data Format */
553 #define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
593 #define HOST_RST 0x8 /* Host Reset */
606 #define DMA_COMPLETE 0x8 /* DMA Complete */
643 #define KPAD_PRESSED 0x8 /* Key press current status */
654 #define XFER_DIR 0x8 /* Transfer Direction */
680 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
692 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
704 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
808 #define RESET 0x8 /* Reset indicator */
819 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
829 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
840 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
850 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
861 #define SOF_B 0x8 /* Start of frame */
872 #define SOF_BE 0x8 /* Start of frame int enable */
891 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
909 #define VBUS0 0x8 /* Vbus level indicator[0] */
920 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
929 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
938 #define DATAEND 0x8 /* Data end indicator */
945 #define SETUPPKT_H 0x8 /* send Setup token host mode */
972 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
995 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1040 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
1051 #define INT_ENA 0x8 /* Interrupt enable */
1075 #define UTE 0x8 /* Urgency Threshold Enable */