Lines Matching refs:bfin_write32
32 #define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
44 #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
46 #define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
48 #define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
50 #define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
53 #define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
55 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
57 #define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
59 #define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
62 #define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
64 #define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
66 #define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
68 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
70 #define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
72 #define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
74 #define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
76 #define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
78 #define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
80 #define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
82 #define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
84 #define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
86 #define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
88 #define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
90 #define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
97 #define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
99 #define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
104 #define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
112 #define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
177 #define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
179 #define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
197 #define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
199 #define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
201 #define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
203 #define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
205 #define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
207 #define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
209 #define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
211 #define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
218 #define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
220 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
224 #define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
226 #define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
233 #define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
235 #define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
237 #define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
239 #define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
241 #define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
243 #define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
252 #define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
254 #define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
256 #define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
258 #define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
260 #define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
262 #define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
264 #define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
266 #define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
268 #define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
270 #define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
272 #define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
274 #define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
276 #define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
278 #define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
280 #define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
282 #define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
284 #define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
286 #define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
288 #define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
290 #define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
292 #define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
294 #define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
296 #define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
298 #define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
300 #define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
312 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
314 #define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
326 #define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
328 #define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
341 #define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
343 #define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
355 #define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
357 #define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
370 #define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
372 #define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
384 #define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
386 #define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
399 #define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
401 #define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
413 #define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
415 #define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
428 #define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
430 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
442 #define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
444 #define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
457 #define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
459 #define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
471 #define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
473 #define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
486 #define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
488 #define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
500 #define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
502 #define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
515 #define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
517 #define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
529 #define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
531 #define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
544 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
546 #define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
558 #define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
560 #define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
573 #define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
575 #define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
587 #define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
589 #define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
602 #define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
604 #define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
616 #define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
618 #define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
631 #define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
633 #define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
645 #define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
647 #define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
660 #define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
662 #define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
674 #define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
676 #define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
686 #define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
688 #define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
700 #define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
702 #define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
715 #define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
717 #define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
729 #define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
731 #define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
741 #define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
743 #define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
755 #define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
757 #define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
786 #define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
788 #define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
790 #define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
792 #define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
794 #define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
796 #define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
801 #define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
803 #define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
805 #define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
807 #define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
809 #define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
811 #define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
813 #define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
815 #define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
817 #define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
819 #define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
824 #define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
826 #define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
828 #define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
830 #define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
832 #define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
834 #define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
836 #define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
838 #define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
840 #define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
842 #define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
847 #define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
849 #define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
851 #define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
853 #define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
855 #define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
857 #define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
859 #define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
861 #define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
863 #define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
865 #define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
870 #define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
872 #define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
874 #define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
876 #define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
878 #define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
880 #define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
882 #define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
884 #define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
886 #define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
888 #define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
907 #define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
926 #define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
945 #define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
964 #define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
983 #define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
1002 #define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1021 #define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1040 #define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1059 #define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1078 #define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1085 #define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1087 #define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1089 #define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1093 #define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1095 #define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1097 #define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1101 #define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1103 #define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1105 #define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1109 #define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1111 #define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1113 #define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1117 #define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1119 #define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1121 #define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1125 #define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1127 #define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1129 #define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1133 #define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1135 #define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1137 #define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1141 #define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1143 #define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1145 #define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1154 #define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1166 #define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
1168 #define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
1180 #define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
1182 #define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
1195 #define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
1197 #define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
1209 #define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
1211 #define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
1224 #define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
1226 #define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
1238 #define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
1240 #define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
1253 #define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
1255 #define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
1267 #define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
1269 #define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
1282 #define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
1284 #define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
1296 #define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
1298 #define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
1311 #define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
1313 #define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
1325 #define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
1327 #define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
1340 #define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
1342 #define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
1354 #define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
1356 #define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
1369 #define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
1371 #define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
1383 #define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
1385 #define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
1398 #define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
1400 #define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
1412 #define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
1414 #define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
1427 #define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
1429 #define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
1441 #define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
1443 #define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
1456 #define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
1458 #define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
1470 #define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
1472 #define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
1485 #define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
1487 #define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
1499 #define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
1501 #define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
1514 #define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
1516 #define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
1528 #define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
1530 #define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
1540 #define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
1542 #define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
1554 #define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
1556 #define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
1569 #define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
1571 #define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
1583 #define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
1585 #define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
1595 #define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
1597 #define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
1609 #define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
1611 #define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
1678 #define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1680 #define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1698 #define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1700 #define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1702 #define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1704 #define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1706 #define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1708 #define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1710 #define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1712 #define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1725 #define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1727 #define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1745 #define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1747 #define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1749 #define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1751 #define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1753 #define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1755 #define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1757 #define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1759 #define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1780 #define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1782 #define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1784 #define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1786 #define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1788 #define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1790 #define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
2612 #define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2614 #define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2616 #define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2621 #define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2665 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2666 bfin_write32(SIC_IWR1, 0);
2667 bfin_write32(SIC_IWR2, 0);
2673 bfin_write32(SIC_IWR0, iwr0);
2674 bfin_write32(SIC_IWR1, iwr1);
2675 bfin_write32(SIC_IWR2, iwr2);
2693 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
2694 bfin_write32(SIC_IWR1, 0);
2695 bfin_write32(SIC_IWR2, 0);
2701 bfin_write32(SIC_IWR0, iwr0);
2702 bfin_write32(SIC_IWR1, iwr1);
2703 bfin_write32(SIC_IWR2, iwr2);