Lines Matching refs:BFIN_IRQ
41 #define BFIN_IRQ(x) ((x) + 7)
43 #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
44 #define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
45 #define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error */
46 #define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Status */
47 #define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Status */
48 #define IRQ_SPI0_ERROR BFIN_IRQ(5) /* SPI0 Status */
49 #define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART0 Status */
50 #define IRQ_RTC BFIN_IRQ(7) /* RTC */
51 #define IRQ_PPI BFIN_IRQ(8) /* DMA Channel 0 (PPI) */
52 #define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA 1 Channel (SPORT0 RX) */
53 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA 2 Channel (SPORT0 TX) */
54 #define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA 3 Channel (SPORT1 RX) */
55 #define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA 4 Channel (SPORT1 TX) */
56 #define IRQ_SPI0 BFIN_IRQ(13) /* DMA 5 Channel (SPI0) */
57 #define IRQ_UART0_RX BFIN_IRQ(14) /* DMA 6 Channel (UART0 RX) */
58 #define IRQ_UART0_TX BFIN_IRQ(15) /* DMA 7 Channel (UART0 TX) */
59 #define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
60 #define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
61 #define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
62 #define IRQ_PORTF_INTA BFIN_IRQ(19) /* Port F Interrupt A */
63 #define IRQ_PORTF_INTB BFIN_IRQ(20) /* Port F Interrupt B */
64 #define IRQ_MEM0_DMA0 BFIN_IRQ(21) /* MDMA0 Stream 0 */
65 #define IRQ_MEM0_DMA1 BFIN_IRQ(22) /* MDMA0 Stream 1 */
66 #define IRQ_WATCH BFIN_IRQ(23) /* Software Watchdog Timer */
67 #define IRQ_DMA1_ERROR BFIN_IRQ(24) /* DMA Error 1 (generic) */
68 #define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Status */
69 #define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Status */
70 #define IRQ_SPI1_ERROR BFIN_IRQ(28) /* SPI1 Status */
71 #define IRQ_SPI2_ERROR BFIN_IRQ(29) /* SPI2 Status */
72 #define IRQ_UART1_ERROR BFIN_IRQ(30) /* UART1 Status */
73 #define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status */
74 #define IRQ_CAN_ERROR BFIN_IRQ(32) /* CAN Status (Error) Interrupt */
75 #define IRQ_SPORT2_RX BFIN_IRQ(33) /* DMA 8 Channel (SPORT2 RX) */
76 #define IRQ_SPORT2_TX BFIN_IRQ(34) /* DMA 9 Channel (SPORT2 TX) */
77 #define IRQ_SPORT3_RX BFIN_IRQ(35) /* DMA 10 Channel (SPORT3 RX) */
78 #define IRQ_SPORT3_TX BFIN_IRQ(36) /* DMA 11 Channel (SPORT3 TX) */
79 #define IRQ_SPI1 BFIN_IRQ(39) /* DMA 14 Channel (SPI1) */
80 #define IRQ_SPI2 BFIN_IRQ(40) /* DMA 15 Channel (SPI2) */
81 #define IRQ_UART1_RX BFIN_IRQ(41) /* DMA 16 Channel (UART1 RX) */
82 #define IRQ_UART1_TX BFIN_IRQ(42) /* DMA 17 Channel (UART1 TX) */
83 #define IRQ_UART2_RX BFIN_IRQ(43) /* DMA 18 Channel (UART2 RX) */
84 #define IRQ_UART2_TX BFIN_IRQ(44) /* DMA 19 Channel (UART2 TX) */
85 #define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 */
86 #define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 */
87 #define IRQ_CAN_RX BFIN_IRQ(47) /* CAN Receive Interrupt */
88 #define IRQ_CAN_TX BFIN_IRQ(48) /* CAN Transmit Interrupt */
89 #define IRQ_MEM1_DMA0 BFIN_IRQ(49) /* MDMA1 Stream 0 */
90 #define IRQ_MEM1_DMA1 BFIN_IRQ(50) /* MDMA1 Stream 1 */
92 #define SYS_IRQS BFIN_IRQ(63) /* 70 */