Lines Matching refs:i_d
31 int i_d, i_i;
39 i_d = i_i = 0;
43 d_tbl[i_d].addr = 0;
44 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
53 d_tbl[i_d].addr = addr;
54 d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
62 d_tbl[i_d].addr = addr;
63 d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
71 d_tbl[i_d].addr = L1_DATA_A_START;
72 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
80 d_tbl[i_d].addr = COREB_L1_DATA_A_START;
81 d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
87 first_switched_dcplb = i_d;
93 while (i_d < MAX_CPLBS)
94 d_tbl[i_d++].data = 0;
102 int i_d, i_i;
104 i_d = 0;
117 dcplb_bounds[i_d].eaddr = uncached_end;
119 dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
120 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
123 dcplb_bounds[i_d].eaddr = _ramend;
124 dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
128 dcplb_bounds[i_d].eaddr = physical_mem_end;
129 dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
133 dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
134 dcplb_bounds[i_d++].data = 0;
136 dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
137 dcplb_bounds[i_d++].data = SDRAM_EBIU;
139 dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
140 dcplb_bounds[i_d++].data = 0;
142 dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
143 dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
146 dcplb_bounds[i_d].eaddr = L2_START;
147 dcplb_bounds[i_d++].data = 0;
149 dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
150 dcplb_bounds[i_d++].data = L2_DMEMORY;
152 dcplb_nr_bounds = i_d;