Lines Matching refs:addr
100 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
110 if (bfin_addr_dcacheable(addr)) {
118 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
119 addr = L2_START;
121 } else if (addr >= physical_mem_end) {
122 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
125 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
132 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
134 addr &= ~(1 * 1024 * 1024 - 1);
139 } else if (addr >= _ramend) {
146 int page = addr >> PAGE_SHIFT;
160 addr &= PAGE_MASK;
161 dcplb_tbl[cpu][idx].addr = addr;
166 bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
174 unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
182 if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
195 unsigned long this_addr = icplb_tbl[cpu][idx].addr;
196 if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
197 addr += PAGE_SIZE;
210 if (addr < _ramend ||
211 (addr < physical_mem_end && reserved_mem_icache_on))
215 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
216 addr = L2_START;
218 } else if (addr >= physical_mem_end) {
219 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
224 int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
233 } else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
235 addr &= ~(1 * 1024 * 1024 - 1);
240 } else if (addr >= _ramend) {
255 int page = addr >> PAGE_SHIFT;
266 addr &= PAGE_MASK;
267 icplb_tbl[cpu][idx].addr = addr;
272 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
342 unsigned long addr = (unsigned long)masks;
354 if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
355 addr = L2_START;
369 dcplb_tbl[cpu][i].addr = addr;
372 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
373 addr += PAGE_SIZE;