Lines Matching refs:boot_cpu_data
266 boot_cpu_data.arch_type = arch_id;
267 boot_cpu_data.cpu_type = cpu_id;
268 boot_cpu_data.arch_revision = arch_rev;
269 boot_cpu_data.cpu_revision = cpu_rev;
270 boot_cpu_data.tlb_config = mmu_type;
271 boot_cpu_data.device_id = device_id;
275 boot_cpu_data.icache.ways = 1 << SYSREG_BFEXT(IASS, config1);
276 boot_cpu_data.icache.sets = 1 << SYSREG_BFEXT(ISET, config1);
277 boot_cpu_data.icache.linesz = 1 << (tmp + 1);
281 boot_cpu_data.dcache.ways = 1 << SYSREG_BFEXT(DASS, config1);
282 boot_cpu_data.dcache.sets = 1 << SYSREG_BFEXT(DSET, config1);
283 boot_cpu_data.dcache.linesz = 1 << (tmp + 1);
293 printk ("CPU: %s chip revision %c\n", get_chip_name(&boot_cpu_data),
294 avr32_get_chip_revision(&boot_cpu_data) + 'A');
322 boot_cpu_data.features = features;
333 icache_size = boot_cpu_data.icache.ways *
334 boot_cpu_data.icache.sets *
335 boot_cpu_data.icache.linesz;
336 dcache_size = boot_cpu_data.dcache.ways *
337 boot_cpu_data.dcache.sets *
338 boot_cpu_data.dcache.linesz;
343 get_chip_name(&boot_cpu_data),
344 avr32_get_chip_revision(&boot_cpu_data) + 'A');
345 if (boot_cpu_data.arch_type < NR_ARCH_NAMES)
347 arch_names[boot_cpu_data.arch_type],
348 boot_cpu_data.arch_revision);
349 if (boot_cpu_data.cpu_type < NR_CPU_NAMES)
351 cpu_names[boot_cpu_data.cpu_type],
352 boot_cpu_data.cpu_revision);
354 freq = (clk_get_rate(boot_cpu_data.clk) + 500) / 1000;
359 boot_cpu_data.icache.ways,
360 boot_cpu_data.icache.sets,
361 boot_cpu_data.icache.linesz);
364 boot_cpu_data.dcache.ways,
365 boot_cpu_data.dcache.sets,
366 boot_cpu_data.dcache.linesz);
370 if (boot_cpu_data.features & (1 << i))
374 boot_cpu_data.loops_per_jiffy / (500000/HZ),
375 (boot_cpu_data.loops_per_jiffy / (5000/HZ)) % 100);