Lines Matching refs:_reg_read
570 static unsigned inline _reg_read( struct nandc_ctrl *ctrl, reg_bit_field_t rbf )
727 _reg_read( ctrl, NANDC_INT_N_REG(irq_off)),
732 if( ! _reg_read( ctrl, NANDC_INT_N_REG(irq_off)))
798 if( _reg_read( ctrl, NANDC_INT_STAT_CTLR_RDY ))
810 0 == _reg_read( ctrl, NANDC_INT_STAT_CTLR_RDY )) {
862 ret = _reg_read(ctrl, NANDC_INT_STAT_FLASH_STATUS);
910 if( !_reg_read( ctrl, NANDC_INT_STAT_SPARE_VALID ) ) {
1039 err_hard_reg = _reg_read(ctrl, NANDC_UNCORR_ERR_COUNT);
1040 err_soft_reg = _reg_read(ctrl, NANDC_READ_CORR_BIT_COUNT);
1093 _reg_read(ctrl, NANDC_UNCORR_ERR_COUNT)){
1094 int era = _reg_read(ctrl,NANDC_INT_STAT_ERASED);
1100 _reg_read(ctrl, NANDC_UNCORR_ERR_COUNT);
1115 _reg_read(ctrl, NANDC_READ_CORR_BIT_COUNT);
1163 nand_addr = _reg_read( ctrl, NANDC_CMD_ADDRESS );
1270 b = _reg_read( ctrl, NANDC_DEVID_BYTE(
1281 b = _reg_read(ctrl, NANDC_INT_STAT_FLASH_STATUS);
1450 sector_1k = _reg_read( ctrl, NANDC_ACC_CTRL_SECTOR_1K(0) );
1451 ecc_level = _reg_read( ctrl, NANDC_ACC_CTRL_ECC_LEVEL(0) );
1578 if( _reg_read( ctrl, NANDC_CONFIG_CHIP_WIDTH(n) ))
1612 _reg_read( ctrl, NANDC_CONFIG_CHIP_SIZE(chip)),
1613 _reg_read( ctrl, NANDC_CONFIG_BLK_SIZE(chip)),
1614 _reg_read( ctrl, NANDC_CONFIG_PAGE_SIZE(chip)),
1615 _reg_read( ctrl, NANDC_ACC_CTRL_ECC_LEVEL(chip))
1657 _reg_read(ctrl, NANDC_REV_MAJOR),
1658 _reg_read(ctrl, NANDC_REV_MINOR)