Lines Matching refs:REG_BIT_FIELD
124 #define REG_BIT_FIELD(r,p,w) ((reg_bit_field_t){(r),(p),(w)})
126 #define NANDC_8KB_PAGE_SUPPORT REG_BIT_FIELD(0x0, 31, 1)
127 #define NANDC_REV_MAJOR REG_BIT_FIELD(0x0, 8, 8)
128 #define NANDC_REV_MINOR REG_BIT_FIELD(0x0, 0, 8)
130 #define NANDC_CMD_START_OPCODE REG_BIT_FIELD(0x4, 24, 5)
132 #define NANDC_CMD_CS_SEL REG_BIT_FIELD(0x8, 16, 3)
133 #define NANDC_CMD_EXT_ADDR REG_BIT_FIELD(0x8, 0, 16)
135 #define NANDC_CMD_ADDRESS REG_BIT_FIELD(0xc, 0, 32)
136 #define NANDC_CMD_END_ADDRESS REG_BIT_FIELD(0x10, 0, 32)
138 #define NANDC_INT_STATUS REG_BIT_FIELD(0x14, 0, 32)
139 #define NANDC_INT_STAT_CTLR_RDY REG_BIT_FIELD(0x14, 31, 1)
140 #define NANDC_INT_STAT_FLASH_RDY REG_BIT_FIELD(0x14, 30, 1)
141 #define NANDC_INT_STAT_CACHE_VALID REG_BIT_FIELD(0x14, 29, 1)
142 #define NANDC_INT_STAT_SPARE_VALID REG_BIT_FIELD(0x14, 28, 1)
143 #define NANDC_INT_STAT_ERASED REG_BIT_FIELD(0x14, 27, 1)
144 #define NANDC_INT_STAT_PLANE_RDY REG_BIT_FIELD(0x14, 26, 1)
145 #define NANDC_INT_STAT_FLASH_STATUS REG_BIT_FIELD(0x14, 0, 8)
147 #define NANDC_CS_LOCK REG_BIT_FIELD(0x18, 31, 1)
148 #define NANDC_CS_AUTO_CONFIG REG_BIT_FIELD(0x18, 30, 1)
149 #define NANDC_CS_NAND_WP REG_BIT_FIELD(0x18, 29, 1)
150 #define NANDC_CS_BLK0_WP REG_BIT_FIELD(0x18, 28, 1)
151 #define NANDC_CS_SW_USING_CS(n) REG_BIT_FIELD(0x18, 8+(n), 1)
152 #define NANDC_CS_MAP_SEL_CS(n) REG_BIT_FIELD(0x18, 0+(n), 1)
154 #define NANDC_XOR_ADDR_BLK0_ONLY REG_BIT_FIELD(0x1c, 31, 1)
155 #define NANDC_XOR_ADDR_CS(n) REG_BIT_FIELD(0x1c, 0+(n), 1)
157 #define NANDC_LL_OP_RET_IDLE REG_BIT_FIELD(0x20, 31, 1)
158 #define NANDC_LL_OP_CLE REG_BIT_FIELD(0x20, 19, 1)
159 #define NANDC_LL_OP_ALE REG_BIT_FIELD(0x20, 18, 1)
160 #define NANDC_LL_OP_WE REG_BIT_FIELD(0x20, 17, 1)
161 #define NANDC_LL_OP_RE REG_BIT_FIELD(0x20, 16, 1)
162 #define NANDC_LL_OP_DATA REG_BIT_FIELD(0x20, 0, 16)
164 #define NANDC_MPLANE_ADDR_EXT REG_BIT_FIELD(0x24, 0, 16)
165 #define NANDC_MPLANE_ADDR REG_BIT_FIELD(0x28, 0, 32)
167 #define NANDC_ACC_CTRL_CS(n) REG_BIT_FIELD(0x50+((n)<<4), 0, 32)
168 #define NANDC_ACC_CTRL_RD_ECC(n) REG_BIT_FIELD(0x50+((n)<<4), 31, 1)
169 #define NANDC_ACC_CTRL_WR_ECC(n) REG_BIT_FIELD(0x50+((n)<<4), 30, 1)
170 #define NANDC_ACC_CTRL_CE_CARE(n) REG_BIT_FIELD(0x50+((n)<<4), 29, 1)
171 #define NANDC_ACC_CTRL_PGM_RDIN(n) REG_BIT_FIELD(0x50+((n)<<4), 28, 1)
172 #define NANDC_ACC_CTRL_ERA_ECC_ERR(n) REG_BIT_FIELD(0x50+((n)<<4), 27, 1)
173 #define NANDC_ACC_CTRL_PGM_PARTIAL(n) REG_BIT_FIELD(0x50+((n)<<4), 26, 1)
174 #define NANDC_ACC_CTRL_WR_PREEMPT(n) REG_BIT_FIELD(0x50+((n)<<4), 25, 1)
175 #define NANDC_ACC_CTRL_PG_HIT(n) REG_BIT_FIELD(0x50+((n)<<4), 24, 1)
176 #define NANDC_ACC_CTRL_PREFETCH(n) REG_BIT_FIELD(0x50+((n)<<4), 23, 1)
177 #define NANDC_ACC_CTRL_CACHE_MODE(n) REG_BIT_FIELD(0x50+((n)<<4), 22, 1)
178 #define NANDC_ACC_CTRL_CACHE_LASTPG(n) REG_BIT_FIELD(0x50+((n)<<4), 21, 1)
179 #define NANDC_ACC_CTRL_ECC_LEVEL(n) REG_BIT_FIELD(0x50+((n)<<4), 16, 5)
180 #define NANDC_ACC_CTRL_SECTOR_1K(n) REG_BIT_FIELD(0x50+((n)<<4), 7, 1)
181 #define NANDC_ACC_CTRL_SPARE_SIZE(n) REG_BIT_FIELD(0x50+((n)<<4), 0, 7)
183 #define NANDC_CONFIG_CS(n) REG_BIT_FIELD(0x54+((n)<<4), 0, 32)
184 #define NANDC_CONFIG_LOCK(n) REG_BIT_FIELD(0x54+((n)<<4), 31, 1)
185 #define NANDC_CONFIG_BLK_SIZE(n) REG_BIT_FIELD(0x54+((n)<<4), 28, 3)
186 #define NANDC_CONFIG_CHIP_SIZE(n) REG_BIT_FIELD(0x54+((n)<<4), 24, 4)
187 #define NANDC_CONFIG_CHIP_WIDTH(n) REG_BIT_FIELD(0x54+((n)<<4), 23, 1)
188 #define NANDC_CONFIG_PAGE_SIZE(n) REG_BIT_FIELD(0x54+((n)<<4), 20, 2)
189 #define NANDC_CONFIG_FUL_ADDR_BYTES(n) REG_BIT_FIELD(0x54+((n)<<4), 16, 3)
190 #define NANDC_CONFIG_COL_ADDR_BYTES(n) REG_BIT_FIELD(0x54+((n)<<4), 12, 3)
191 #define NANDC_CONFIG_BLK_ADDR_BYTES(n) REG_BIT_FIELD(0x54+((n)<<4), 8, 3)
193 #define NANDC_TIMING_1_CS(n) REG_BIT_FIELD(0x58+((n)<<4), 0, 32)
194 #define NANDC_TIMING_2_CS(n) REG_BIT_FIELD(0x5c+((n)<<4), 0, 32)
197 #define NANDC_CORR_STAT_THRESH_CS(n) REG_BIT_FIELD(0xc0, 6*(n), 6)
199 #define NANDC_BLK_WP_END_ADDR REG_BIT_FIELD(0xc8, 0, 32)
201 #define NANDC_MPLANE_ERASE_CYC2_OPCODE REG_BIT_FIELD(0xcc, 24, 8)
202 #define NANDC_MPLANE_READ_STAT_OPCODE REG_BIT_FIELD(0xcc, 16, 8)
203 #define NANDC_MPLANE_PROG_ODD_OPCODE REG_BIT_FIELD(0xcc, 8, 8)
204 #define NANDC_MPLANE_PROG_TRL_OPCODE REG_BIT_FIELD(0xcc, 0, 8)
206 #define NANDC_MPLANE_PGCACHE_TRL_OPCODE REG_BIT_FIELD(0xd0, 24, 8)
207 #define NANDC_MPLANE_READ_STAT2_OPCODE REG_BIT_FIELD(0xd0, 16, 8)
208 #define NANDC_MPLANE_READ_EVEN_OPCODE REG_BIT_FIELD(0xd0, 8, 8)
209 #define NANDC_MPLANE_READ_ODD__OPCODE REG_BIT_FIELD(0xd0, 0, 8)
211 #define NANDC_MPLANE_CTRL_ERASE_CYC2_EN REG_BIT_FIELD(0xd4, 31, 1)
212 #define NANDC_MPLANE_CTRL_RD_ADDR_SIZE REG_BIT_FIELD(0xd4, 30, 1)
213 #define NANDC_MPLANE_CTRL_RD_CYC_ADDR REG_BIT_FIELD(0xd4, 29, 1)
214 #define NANDC_MPLANE_CTRL_RD_COL_ADDR REG_BIT_FIELD(0xd4, 28, 1)
216 #define NANDC_UNCORR_ERR_COUNT REG_BIT_FIELD(0xfc, 0, 32)
218 #define NANDC_CORR_ERR_COUNT REG_BIT_FIELD(0x100, 0, 32)
220 #define NANDC_READ_CORR_BIT_COUNT REG_BIT_FIELD(0x104, 0, 32)
222 #define NANDC_BLOCK_LOCK_STATUS REG_BIT_FIELD(0x108, 0, 8)
224 #define NANDC_ECC_CORR_ADDR_CS REG_BIT_FIELD(0x10c, 16, 3)
225 #define NANDC_ECC_CORR_ADDR_EXT REG_BIT_FIELD(0x10c, 0, 16)
227 #define NANDC_ECC_CORR_ADDR REG_BIT_FIELD(0x110, 0, 32)
229 #define NANDC_ECC_UNC_ADDR_CS REG_BIT_FIELD(0x114, 16, 3)
230 #define NANDC_ECC_UNC_ADDR_EXT REG_BIT_FIELD(0x114, 0, 16)
232 #define NANDC_ECC_UNC_ADDR REG_BIT_FIELD(0x118, 0, 32)
234 #define NANDC_READ_ADDR_CS REG_BIT_FIELD(0x11c, 16, 3)
235 #define NANDC_READ_ADDR_EXT REG_BIT_FIELD(0x11c, 0, 16)
236 #define NANDC_READ_ADDR REG_BIT_FIELD(0x120, 0, 32)
238 #define NANDC_PROG_ADDR_CS REG_BIT_FIELD(0x124, 16, 3)
239 #define NANDC_PROG_ADDR_EXT REG_BIT_FIELD(0x124, 0, 16)
240 #define NANDC_PROG_ADDR REG_BIT_FIELD(0x128, 0, 32)
242 #define NANDC_CPYBK_ADDR_CS REG_BIT_FIELD(0x12c, 16, 3)
243 #define NANDC_CPYBK_ADDR_EXT REG_BIT_FIELD(0x12c, 0, 16)
244 #define NANDC_CPYBK_ADDR REG_BIT_FIELD(0x130, 0, 32)
246 #define NANDC_ERASE_ADDR_CS REG_BIT_FIELD(0x134, 16, 3)
247 #define NANDC_ERASE_ADDR_EXT REG_BIT_FIELD(0x134, 0, 16)
248 #define NANDC_ERASE_ADDR REG_BIT_FIELD(0x138, 0, 32)
250 #define NANDC_INV_READ_ADDR_CS REG_BIT_FIELD(0x13c, 16, 3)
251 #define NANDC_INV_READ_ADDR_EXT REG_BIT_FIELD(0x13c, 0, 16)
252 #define NANDC_INV_READ_ADDR REG_BIT_FIELD(0x140, 0, 32)
254 #define NANDC_INIT_STAT REG_BIT_FIELD(0x144, 0, 32)
255 #define NANDC_INIT_ONFI_DONE REG_BIT_FIELD(0x144, 31, 1)
256 #define NANDC_INIT_DEVID_DONE REG_BIT_FIELD(0x144, 30, 1)
257 #define NANDC_INIT_SUCCESS REG_BIT_FIELD(0x144, 29, 1)
258 #define NANDC_INIT_FAIL REG_BIT_FIELD(0x144, 28, 1)
259 #define NANDC_INIT_BLANK REG_BIT_FIELD(0x144, 27, 1)
260 #define NANDC_INIT_TIMEOUT REG_BIT_FIELD(0x144, 26, 1)
261 #define NANDC_INIT_UNC_ERROR REG_BIT_FIELD(0x144, 25, 1)
262 #define NANDC_INIT_CORR_ERROR REG_BIT_FIELD(0x144, 24, 1)
263 #define NANDC_INIT_PARAM_RDY REG_BIT_FIELD(0x144, 23, 1)
264 #define NANDC_INIT_AUTH_FAIL REG_BIT_FIELD(0x144, 22, 1)
266 #define NANDC_ONFI_STAT REG_BIT_FIELD(0x148, 0, 32)
267 #define NANDC_ONFI_DEBUG REG_BIT_FIELD(0x148, 28, 4)
268 #define NANDC_ONFI_PRESENT REG_BIT_FIELD(0x148, 27, 1)
269 #define NANDC_ONFI_BADID_PG2 REG_BIT_FIELD(0x148, 5, 1)
270 #define NANDC_ONFI_BADID_PG1 REG_BIT_FIELD(0x148, 4, 1)
271 #define NANDC_ONFI_BADID_PG0 REG_BIT_FIELD(0x148, 3, 1)
272 #define NANDC_ONFI_BADCRC_PG2 REG_BIT_FIELD(0x148, 2, 1)
273 #define NANDC_ONFI_BADCRC_PG1 REG_BIT_FIELD(0x148, 1, 1)
274 #define NANDC_ONFI_BADCRC_PG0 REG_BIT_FIELD(0x148, 0, 1)
276 #define NANDC_ONFI_DEBUG_DATA REG_BIT_FIELD(0x14c, 0, 32)
278 #define NANDC_SEMAPHORE REG_BIT_FIELD(0x150, 0, 8)
280 #define NANDC_DEVID_BYTE(b) REG_BIT_FIELD(0x194+((b)&0x4), \
283 #define NANDC_LL_RDDATA REG_BIT_FIELD(0x19c, 0, 16)
285 #define NANDC_INT_N_REG(n) REG_BIT_FIELD(0xf00|((n)<<2), 0, 1)
286 #define NANDC_INT_DIREC_READ_MISS REG_BIT_FIELD(0xf00, 0, 1)
287 #define NANDC_INT_ERASE_DONE REG_BIT_FIELD(0xf04, 0, 1)
288 #define NANDC_INT_CPYBK_DONE REG_BIT_FIELD(0xf08, 0, 1)
289 #define NANDC_INT_PROGRAM_DONE REG_BIT_FIELD(0xf0c, 0, 1)
290 #define NANDC_INT_CONTROLLER_RDY REG_BIT_FIELD(0xf10, 0, 1)
291 #define NANDC_INT_RDBSY_RDY REG_BIT_FIELD(0xf14, 0, 1)
292 #define NANDC_INT_ECC_UNCORRECTABLE REG_BIT_FIELD(0xf18, 0, 1)
293 #define NANDC_INT_ECC_CORRECTABLE REG_BIT_FIELD(0xf1c, 0, 1)