Lines Matching refs:_reg_write
345 static void inline _reg_write( struct net_device *dev,
536 _reg_write( dev, UMAC_CONFIG_PROMISC, 1);
538 _reg_write( dev, UMAC_CONFIG_PROMISC, 0);
553 _reg_write( dev, UMAC_MACADDR_LOW, hw_addr[0] );
554 _reg_write( dev, UMAC_MACADDR_HIGH, hw_addr[1] );
632 _reg_write( dev, GMAC_INTMASN, 0 );
638 _reg_write( dev, GMAC_INTMASN, int_msk );
840 _reg_write( dev, GMAC_RX_PTR, priv->rx_desc_paddr + off);
875 _reg_write( dev, GMAC_INTMASK_RX_INT, 1);
895 _reg_write( dev, GMAC_INTMASK_TX_INT(q), 1);
929 _reg_write( dev, GMAC_INTMASK_RX_INT, 0);
930 _reg_write( dev, GMAC_INTSTAT_RX_INT, 1);
938 _reg_write( dev, GMAC_TIMER, 0 );
939 _reg_write( dev, GMAC_INTMASK_TIMER_INT, 0);
940 _reg_write( dev, GMAC_INTSTAT_TIMER_INT, 1);
941 _reg_write( dev, GMAC_INTMASK_TX_INT(q), 0);
942 _reg_write( dev, GMAC_INTSTAT_TX_INT(q), 1);
949 _reg_write( dev, GMAC_INTSTAT_MII_LINK_CHANGE, 1);
953 _reg_write( dev, GMAC_INTSTAT_SW_LINK_CHANGE, 1);
963 _reg_write( dev, GMAC_INTSTAT_DMA_DATA_ERR, 1);
968 _reg_write( dev, GMAC_INTSTAT_DMA_PROTO_ERR, 1);
974 _reg_write( dev, GMAC_INTSTAT_DMA_RX_UNDERFLOW, 1);
980 _reg_write( dev, GMAC_INTSTAT_DMA_RX_OVERFLOW, 1);
985 _reg_write( dev, GMAC_INTSTAT_DMA_TX_UNDERFLOW, 1);
1139 _reg_write( dev, GMAC_TXCTL_SUSPEND(q), 1);
1159 _reg_write( dev, GMAC_TXCTL_SUSPEND(q), 0);
1162 _reg_write( dev, GMAC_TX_PTR(q), priv->tx_desc_paddr + off);
1166 _reg_write( dev, GMAC_TIMER, 500000000 );
1167 _reg_write( dev, GMAC_INTSTAT_TIMER_INT, 1);
1168 _reg_write( dev, GMAC_INTMASK_TIMER_INT, 1);
1265 _reg_write( dev, GMAC_RX_ADDR_LOW, priv->rx_desc_paddr );
1266 _reg_write( dev, GMAC_RX_ADDR_HIGH, (u64)priv->rx_desc_paddr >> 32);
1267 _reg_write( dev, GMAC_TX_ADDR_LOW(q), priv->tx_desc_paddr );
1268 _reg_write( dev, GMAC_TX_ADDR_HIGH(q), (u64)priv->tx_desc_paddr >> 32);
1271 _reg_write( dev, GMAC_RXCTL, 0);
1272 _reg_write( dev, GMAC_RXCTL_RX_OFFSET, sizeof( gmac_rxstat_t ));
1273 _reg_write( dev, GMAC_RXCTL_OFLOW_CONT, 1);
1274 _reg_write( dev, GMAC_RXCTL_PARITY_DIS, 0);
1275 _reg_write( dev, GMAC_RXCTL_BURST_LEN, 1); /* 32-bytes */
1283 _reg_write( dev, UMAC_FRM_LENGTH, AMAC_MAX_PACKET);
1285 _reg_write( dev, UMAC_CONFIG_ETH_SPEED, 2); /* 1Gbps */
1286 _reg_write( dev, UMAC_CONFIG_CRC_FW, 0);
1287 _reg_write( dev, UMAC_CONFIG_LNGTHCHK_DIS, 1);
1288 _reg_write( dev, UMAC_CONFIG_CNTLFRM_EN, 0);
1289 _reg_write( dev, UMAC_CONFIG_PROMISC, 0);
1290 _reg_write( dev, UMAC_CONFIG_LCL_LOOP_EN, 0);
1291 _reg_write( dev, UMAC_CONFIG_RMT_LOOP_EN, 0);
1292 _reg_write( dev, UMAC_CONFIG_TXRX_AUTO_EN, 0);
1293 _reg_write( dev, UMAC_CONFIG_AUTO_EN, 0);
1294 _reg_write( dev, UMAC_CONFIG_TX_ADDR_INS, 0);
1295 _reg_write( dev, UMAC_CONFIG_PAD_EN, 0);
1296 _reg_write( dev, UMAC_CONFIG_PREAMB_EN, 0);
1297 _reg_write( dev, UMAC_CONFIG_TX_EN, 1);
1298 _reg_write( dev, UMAC_CONFIG_RX_EN, 1);
1301 _reg_write( dev, GMAC_CTL_FLOW_CNTLSRC, 0);
1302 _reg_write( dev, GMAC_CTL_RX_OVFLOW_MODE, 0);
1303 _reg_write( dev, GMAC_CTL_MIB_RESET, 0);
1304 _reg_write( dev, GMAC_CTL_LINKSTAT_SEL, 1);
1305 _reg_write( dev, GMAC_CTL_FLOW_CNTL_MODE, 0);
1306 _reg_write( dev, GMAC_CTL_NWAY_AUTO_POLL, 1);
1309 _reg_write( dev, GMAC_TXCTL(q), 0);
1310 _reg_write( dev, GMAC_TXCTL_PARITY_DIS(q), 0);
1311 _reg_write( dev, GMAC_TXCTL_BURST_LEN(q), 1); /* 32-bytes */
1312 _reg_write( dev, GMAC_TXCTL_DNA_ACT_INDEX(q), 1);/* for debug */
1315 _reg_write( dev, GMAC_TXCTL_TX_EN(q), 1);
1318 _reg_write( dev, GMAC_RXCTL_RX_EN, 1);
1332 _reg_write( dev, GMAC_INTMASK_RX_INT, 1);
1333 _reg_write( dev, GMAC_INTMASK_TX_INT(q), 1);
1334 _reg_write( dev, GMAC_INTMASK_MII_LINK_CHANGE, 1);
1335 _reg_write( dev, GMAC_INTMASK_SW_LINK_CHANGE, 1);
1336 _reg_write( dev, GMAC_INTMASK_DMA_DESC_ERR, 1);
1337 _reg_write( dev, GMAC_INTMASK_DMA_DATA_ERR, 1);
1338 _reg_write( dev, GMAC_INTMASK_DMA_PROTO_ERR, 1);
1339 _reg_write( dev, GMAC_INTMASK_DMA_RX_UNDERFLOW, 1);
1340 _reg_write( dev, GMAC_INTMASK_DMA_RX_OVERFLOW, 1);
1341 _reg_write( dev, GMAC_INTMASK_DMA_TX_UNDERFLOW, 1);
1342 /* _reg_write( dev, GMAC_INTMASK_TIMER_INT, 1); */
1345 _reg_write( dev, GMAC_INTRX_LZY_TIMEOUT, 125000 );
1346 _reg_write( dev, GMAC_INTRX_LZY_FRMCNT, 16 );
1388 _reg_write( dev, GMAC_CTL_TX_FLUSH, 1);
1395 _reg_write( dev, GMAC_RXCTL_RX_EN, 0);
1398 _reg_write( dev, GMAC_TXCTL_TX_EN(q), 0);
1401 _reg_write( dev, GMAC_INTMASK, 0);
1412 _reg_write( dev, UMAC_CONFIG_TX_EN, 0);
1413 _reg_write( dev, UMAC_CONFIG_RX_EN, 0);
1414 _reg_write( dev, UMAC_CONFIG_SW_RESET, 1);
1467 _reg_write( dev, UMAC_CONFIG_SW_RESET, 0);