Lines Matching refs:REG_BIT_FIELD
73 #define REG_BIT_FIELD(r,p,w) ((reg_bit_field_t){(r),(p),(w)})
75 #define GMAC_CTL_TX_ARB_MODE REG_BIT_FIELD(0x0, 0, 1)
76 #define GMAC_CTL_RX_OVFLOW_MODE REG_BIT_FIELD(0x0, 1, 1)
77 #define GMAC_CTL_FLOW_CNTLSRC REG_BIT_FIELD(0x0, 2, 1)
78 #define GMAC_CTL_LINKSTAT_SEL REG_BIT_FIELD(0x0, 3, 1)
79 #define GMAC_CTL_MIB_RESET REG_BIT_FIELD(0x0, 4, 1)
80 #define GMAC_CTL_FLOW_CNTL_MODE REG_BIT_FIELD(0x0, 5, 2)
81 #define GMAC_CTL_NWAY_AUTO_POLL REG_BIT_FIELD(0x0, 7, 1)
82 #define GMAC_CTL_TX_FLUSH REG_BIT_FIELD(0x0, 8, 1)
83 #define GMAC_CTL_RXCLK_DMG REG_BIT_FIELD(0x0, 16, 2)
84 #define GMAC_CTL_TXCLK_DMG REG_BIT_FIELD(0x0, 18, 2)
85 #define GMAC_CTL_RXCLK_DLL REG_BIT_FIELD(0x0, 20, 1)
86 #define GMAC_CTL_TXCLK_DLL REG_BIT_FIELD(0x0, 21, 1)
88 #define GMAC_STAT REG_BIT_FIELD(0x04, 0, 32)
89 #define GMAC_STAT_RX_FIFO_FULL REG_BIT_FIELD(0x04, 0, 1)
90 #define GMAC_STAT_RX_DBUF_FULL REG_BIT_FIELD(0x04, 1, 1)
91 #define GMAC_STAT_RX_IBUF_FULL REG_BIT_FIELD(0x04, 2, 1)
92 #define GMAC_STAT_TX_FIFO_FULL REG_BIT_FIELD(0x04, 3, 1)
93 #define GMAC_STAT_TX_DBUF_FULL REG_BIT_FIELD(0x04, 4, 1)
94 #define GMAC_STAT_TX_IBUF_FULL REG_BIT_FIELD(0x04, 5, 1)
95 #define GMAC_STAT_TX_PAUSE REG_BIT_FIELD(0x04, 6, 1)
96 #define GMAC_STAT_TX_IF_MODE REG_BIT_FIELD(0x04, 7, 2)
97 #define GMAC_STAT_RX_Q_SIZE REG_BIT_FIELD(0x04, 16, 4)
98 #define GMAC_STAT_TX_Q_SIZE REG_BIT_FIELD(0x04, 20, 4)
100 #define GMAC_INTSTAT REG_BIT_FIELD(0x020, 0, 32)
101 #define GMAC_INTSTAT_MIB_RX_OVRUN REG_BIT_FIELD(0x020, 0, 1)
102 #define GMAC_INTSTAT_MIB_TX_OVRUN REG_BIT_FIELD(0x020, 1, 1)
103 #define GMAC_INTSTAT_TX_FLUSH_DONE REG_BIT_FIELD(0x020, 2, 1)
104 #define GMAC_INTSTAT_MII_LINK_CHANGE REG_BIT_FIELD(0x020, 3, 1)
105 #define GMAC_INTSTAT_MDIO_DONE REG_BIT_FIELD(0x020, 4, 1)
106 #define GMAC_INTSTAT_MIB_RX_HALF REG_BIT_FIELD(0x020, 5, 1)
107 #define GMAC_INTSTAT_MIB_TX_HALF REG_BIT_FIELD(0x020, 6, 1)
108 #define GMAC_INTSTAT_TIMER_INT REG_BIT_FIELD(0x020, 7, 1)
109 #define GMAC_INTSTAT_SW_LINK_CHANGE REG_BIT_FIELD(0x020, 8, 1)
110 #define GMAC_INTSTAT_DMA_DESC_ERR REG_BIT_FIELD(0x020, 10, 1)
111 #define GMAC_INTSTAT_DMA_DATA_ERR REG_BIT_FIELD(0x020, 11, 1)
112 #define GMAC_INTSTAT_DMA_PROTO_ERR REG_BIT_FIELD(0x020, 12, 1)
113 #define GMAC_INTSTAT_DMA_RX_UNDERFLOW REG_BIT_FIELD(0x020, 13, 1)
114 #define GMAC_INTSTAT_DMA_RX_OVERFLOW REG_BIT_FIELD(0x020, 14, 1)
115 #define GMAC_INTSTAT_DMA_TX_UNDERFLOW REG_BIT_FIELD(0x020, 15, 1)
116 #define GMAC_INTSTAT_RX_INT REG_BIT_FIELD(0x020, 16, 1)
117 #define GMAC_INTSTAT_TX_INT(q) REG_BIT_FIELD(0x020, 24+(q), 1)
118 #define GMAC_INTSTAT_RX_ECC_SOFT REG_BIT_FIELD(0x020, 28, 1)
119 #define GMAC_INTSTAT_RX_ECC_HARD REG_BIT_FIELD(0x020, 29, 1)
120 #define GMAC_INTSTAT_TX_ECC_SOFT REG_BIT_FIELD(0x020, 30, 1)
121 #define GMAC_INTSTAT_TX_ECC_HARD REG_BIT_FIELD(0x020, 31, 1)
123 #define GMAC_INTMASK REG_BIT_FIELD(0x024, 0, 32)
124 #define GMAC_INTMASK_MIB_RX_OVRUN REG_BIT_FIELD(0x024, 0, 1)
125 #define GMAC_INTMASK_MIB_TX_OVRUN REG_BIT_FIELD(0x024, 1, 1)
126 #define GMAC_INTMASK_TX_FLUSH_DONE REG_BIT_FIELD(0x024, 2, 1)
127 #define GMAC_INTMASK_MII_LINK_CHANGE REG_BIT_FIELD(0x024, 3, 1)
128 #define GMAC_INTMASK_MDIO_DONE REG_BIT_FIELD(0x024, 4, 1)
129 #define GMAC_INTMASK_MIB_RX_HALF REG_BIT_FIELD(0x024, 5, 1)
130 #define GMAC_INTMASK_MIB_TX_HALF REG_BIT_FIELD(0x024, 6, 1)
131 #define GMAC_INTMASK_TIMER_INT REG_BIT_FIELD(0x024, 7, 1)
132 #define GMAC_INTMASK_SW_LINK_CHANGE REG_BIT_FIELD(0x024, 8, 1)
133 #define GMAC_INTMASK_DMA_DESC_ERR REG_BIT_FIELD(0x024, 10, 1)
134 #define GMAC_INTMASK_DMA_DATA_ERR REG_BIT_FIELD(0x024, 11, 1)
135 #define GMAC_INTMASK_DMA_PROTO_ERR REG_BIT_FIELD(0x024, 12, 1)
136 #define GMAC_INTMASK_DMA_RX_UNDERFLOW REG_BIT_FIELD(0x024, 13, 1)
137 #define GMAC_INTMASK_DMA_RX_OVERFLOW REG_BIT_FIELD(0x024, 14, 1)
138 #define GMAC_INTMASK_DMA_TX_UNDERFLOW REG_BIT_FIELD(0x024, 15, 1)
139 #define GMAC_INTMASK_RX_INT REG_BIT_FIELD(0x024, 16, 1)
140 #define GMAC_INTMASK_TX_INT(q) REG_BIT_FIELD(0x024, 24+(q), 1)
141 #define GMAC_INTMASK_RX_ECC_SOFT REG_BIT_FIELD(0x024, 28, 1)
142 #define GMAC_INTMASK_RX_ECC_HARD REG_BIT_FIELD(0x024, 29, 1)
143 #define GMAC_INTMASK_TX_ECC_SOFT REG_BIT_FIELD(0x024, 30, 1)
144 #define GMAC_INTMASK_TX_ECC_HARD REG_BIT_FIELD(0x024, 31, 1)
146 #define GMAC_TIMER REG_BIT_FIELD(0x028, 0, 32)
148 #define GMAC_INTRX_LZY_TIMEOUT REG_BIT_FIELD(0x100,0,24)
149 #define GMAC_INTRX_LZY_FRMCNT REG_BIT_FIELD(0x100,24,8)
151 #define GMAC_PHYACC_DATA REG_BIT_FIELD(0x180, 0, 16)
152 #define GMAC_PHYACC_ADDR REG_BIT_FIELD(0x180, 16, 5)
153 #define GMAC_PHYACC_REG REG_BIT_FIELD(0x180, 24, 5)
154 #define GMAC_PHYACC_WRITE REG_BIT_FIELD(0x180, 29, 1)
155 #define GMAC_PHYACC_GO REG_BIT_FIELD(0x180, 30, 1)
157 #define GMAC_PHYCTL_ADDR REG_BIT_FIELD(0x188, 0, 5)
158 #define GMAC_PHYCTL_MDC_CYCLE REG_BIT_FIELD(0x188, 16, 7)
159 #define GMAC_PHYCTL_MDC_TRANS REG_BIT_FIELD(0x188, 23, 1)
162 #define GMAC_TXCTL(q) REG_BIT_FIELD(0x200+((q)<<6),0,32)
163 #define GMAC_TXCTL_TX_EN(q) REG_BIT_FIELD(0x200+((q)<<6),0,1)
164 #define GMAC_TXCTL_SUSPEND(q) REG_BIT_FIELD(0x200+((q)<<6),1,1)
165 #define GMAC_TXCTL_DMALOOPBACK(q) REG_BIT_FIELD(0x200+((q)<<6),2,1)
166 #define GMAC_TXCTL_DESC_ALIGN(q) REG_BIT_FIELD(0x200+((q)<<6),5,1)
167 #define GMAC_TXCTL_OUTSTAND_READS(q) REG_BIT_FIELD(0x200+((q)<<6),6,2)
168 #define GMAC_TXCTL_PARITY_DIS(q) REG_BIT_FIELD(0x200+((q)<<6),11,1)
169 #define GMAC_TXCTL_DNA_ACT_INDEX(q) REG_BIT_FIELD(0x200+((q)<<6),13,1)
170 #define GMAC_TXCTL_EXTADDR(q) REG_BIT_FIELD(0x200+((q)<<6),16,2)
171 #define GMAC_TXCTL_BURST_LEN(q) REG_BIT_FIELD(0x200+((q)<<6),18,3)
172 #define GMAC_TXCTL_PFETCH_CTL(q) REG_BIT_FIELD(0x200+((q)<<6),21,3)
173 #define GMAC_TXCTL_PFETCH_TH(q) REG_BIT_FIELD(0x200+((q)<<6),24,2)
175 #define GMAC_TX_PTR(q) REG_BIT_FIELD(0x204+((q)<<6),0,12)
176 #define GMAC_TX_ADDR_LOW(q) REG_BIT_FIELD(0x208+((q)<<6),0,32)
177 #define GMAC_TX_ADDR_HIGH(q) REG_BIT_FIELD(0x20c+((q)<<6),0,32)
178 #define GMAC_TXSTAT_CURR_DESC(q) REG_BIT_FIELD(0x210+((q)<<6),0,12)
179 #define GMAC_TXSTAT_TXSTATE(q) REG_BIT_FIELD(0x210+((q)<<6),28,4)
180 #define GMAC_TXSTAT_ACT_DESC(q) REG_BIT_FIELD(0x214+((q)<<6),0,12)
181 #define GMAC_TXSTAT_TXERR(q) REG_BIT_FIELD(0x214+((q)<<6),28,4)
183 #define GMAC_RXCTL REG_BIT_FIELD(0x220,0,32)
184 #define GMAC_RXCTL_RX_EN REG_BIT_FIELD(0x220,0,1)
185 #define GMAC_RXCTL_RX_OFFSET REG_BIT_FIELD(0x220,1,7)
186 #define GMAC_RXCTL_SEP_HDR_DESC REG_BIT_FIELD(0x220,9,1)
187 #define GMAC_RXCTL_OFLOW_CONT REG_BIT_FIELD(0x220,10,1)
188 #define GMAC_RXCTL_PARITY_DIS REG_BIT_FIELD(0x220,11,1)
189 #define GMAC_RXCTL_WAIT_COMPLETE REG_BIT_FIELD(0x220,12,1)
190 #define GMAC_RXCTL_DMA_ACT_INDEX REG_BIT_FIELD(0x220,13,1)
191 #define GMAC_RXCTL_EXTADDR REG_BIT_FIELD(0x220,16,2)
192 #define GMAC_RXCTL_BURST_LEN REG_BIT_FIELD(0x220,18,3)
193 #define GMAC_RXCTL_PFETCH_CTL REG_BIT_FIELD(0x220,21,3)
194 #define GMAC_RXCTL_PFETCH_TH REG_BIT_FIELD(0x220,24,2)
195 #define GMAC_RX_PTR REG_BIT_FIELD(0x224,0,12)
196 #define GMAC_RX_ADDR_LOW REG_BIT_FIELD(0x228,0,32)
197 #define GMAC_RX_ADDR_HIGH REG_BIT_FIELD(0x22c,0,32)
198 #define GMAC_RXSTAT_CURR_DESC REG_BIT_FIELD(0x230,0,12)
199 #define GMAC_RXSTAT_RXSTATE REG_BIT_FIELD(0x230,28,4)
200 #define GMAC_RXSTAT_ACT_DESC REG_BIT_FIELD(0x234,0,12)
201 #define GMAC_RXSTAT_RXERR REG_BIT_FIELD(0x234,28,4)
203 #define UMAC_CORE_VERSION REG_BIT_FIELD(0x800,0,32)
204 #define UMAC_HD_FC_ENA REG_BIT_FIELD(0x804,0,1)
205 #define UMAC_HD_FC_NKOFF REG_BIT_FIELD(0x804,1,1)
206 #define UMAC_IPG_CONFIG_RX REG_BIT_FIELD(0x804,2,5)
208 #define UMAC_CONFIG REG_BIT_FIELD(0x808,0,32)
209 #define UMAC_CONFIG_TX_EN REG_BIT_FIELD(0x808,0,1)
210 #define UMAC_CONFIG_RX_EN REG_BIT_FIELD(0x808,1,1)
211 #define UMAC_CONFIG_ETH_SPEED REG_BIT_FIELD(0x808,2,2)
212 #define UMAC_CONFIG_PROMISC REG_BIT_FIELD(0x808,4,1)
213 #define UMAC_CONFIG_PAD_EN REG_BIT_FIELD(0x808,5,1)
214 #define UMAC_CONFIG_CRC_FW REG_BIT_FIELD(0x808,6,1)
215 #define UMAC_CONFIG_PAUSE_FW REG_BIT_FIELD(0x808,7,1)
216 #define UMAC_CONFIG_RX_PAUSE_IGN REG_BIT_FIELD(0x808,8,1)
217 #define UMAC_CONFIG_TX_ADDR_INS REG_BIT_FIELD(0x808,9,1)
218 #define UMAC_CONFIG_HD_ENA REG_BIT_FIELD(0x808,10,1)
219 #define UMAC_CONFIG_SW_RESET REG_BIT_FIELD(0x808,11,1)
220 #define UMAC_CONFIG_LCL_LOOP_EN REG_BIT_FIELD(0x808,15,1)
221 #define UMAC_CONFIG_AUTO_EN REG_BIT_FIELD(0x808,22,1)
222 #define UMAC_CONFIG_CNTLFRM_EN REG_BIT_FIELD(0x808,23,1)
223 #define UMAC_CONFIG_LNGTHCHK_DIS REG_BIT_FIELD(0x808,24,1)
224 #define UMAC_CONFIG_RMT_LOOP_EN REG_BIT_FIELD(0x808,25,1)
225 #define UMAC_CONFIG_PREAMB_EN REG_BIT_FIELD(0x808,27,1)
226 #define UMAC_CONFIG_TX_PAUSE_IGN REG_BIT_FIELD(0x808,28,1)
227 #define UMAC_CONFIG_TXRX_AUTO_EN REG_BIT_FIELD(0x808,29,1)
229 #define UMAC_MACADDR_LOW REG_BIT_FIELD(0x80c,0,32)
230 #define UMAC_MACADDR_HIGH REG_BIT_FIELD(0x810,0,16)
231 #define UMAC_FRM_LENGTH REG_BIT_FIELD(0x814,0,14)
232 #define UMAC_PAUSE_QUANT REG_BIT_FIELD(0x818,0,16)
234 #define UMAC_MAC_STAT REG_BIT_FIELD(0x844,0,32)
235 #define UMAC_MAC_SPEED REG_BIT_FIELD(0x844,0,2)
236 #define UMAC_MAC_DUPLEX REG_BIT_FIELD(0x844,2,1)
237 #define UMAC_MAC_RX_PAUSE REG_BIT_FIELD(0x844,3,1)
238 #define UMAC_MAC_TX_PAUSE REG_BIT_FIELD(0x844,4,1)
239 #define UMAC_MAC_LINK REG_BIT_FIELD(0x844,5,1)
241 #define UMAC_FRM_TAG0 REG_BIT_FIELD(0x848,0,16)
242 #define UMAC_FRM_TAG1 REG_BIT_FIELD(0x84c,0,16)
243 #define UMAC_IPG_CONFIG_TX REG_BIT_FIELD(0x85c,0,5)
245 #define UMAC_PAUSE_TIMER REG_BIT_FIELD(0xb30,0,17)
246 #define UMAC_PAUSE_CONTROL_EN REG_BIT_FIELD(0xb30,17,1)
247 #define UMAC_TXFIFO_FLUSH REG_BIT_FIELD(0xb34,0,1)
248 #define UMAC_RXFIFO_STAT REG_BIT_FIELD(0xb38,0,2)