Lines Matching refs:r0
93 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
94 bic r0, r0, #0x1800 @ ...IZ...........
95 bic r0, r0, #0x0006 @ .............CA.
96 mcr p15, 0, r0, c1, c0, 0 @ disable caches
122 mov pc, r0
137 mov r0, #1
138 mcr p14, 0, r0, c7, c0, 0 @ go to idle
161 clean_d_cache r0, r1
181 sub r3, r1, r0 @ calculate total size
186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
187 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
188 add r0, r0, #CACHELINESIZE
189 cmp r0, r1
213 bic r0, r0, #CACHELINESIZE - 1
214 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
215 add r0, r0, #CACHELINESIZE
216 cmp r0, r1
218 mov r0, #0
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
220 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
221 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
234 add r1, r0, r1
235 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
236 add r0, r0, #CACHELINESIZE
237 cmp r0, r1
239 mov r0, #0
240 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
241 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
242 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
257 tst r0, #CACHELINESIZE - 1
258 bic r0, r0, #CACHELINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
262 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
263 add r0, r0, #CACHELINESIZE
264 cmp r0, r1
266 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
278 bic r0, r0, #CACHELINESIZE - 1
279 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
280 add r0, r0, #CACHELINESIZE
281 cmp r0, r1
283 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
295 bic r0, r0, #CACHELINESIZE - 1
296 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
297 add r0, r0, #CACHELINESIZE
298 cmp r0, r1
300 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
310 add r1, r1, r0
339 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
340 add r0, r0, #CACHELINESIZE
360 orr r0, r0, #0x18 @ cache the page table in L2
361 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
411 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
412 msr cpsr_c, r0
420 mov r0, #1 << 6 @ cp6 access for early sched_clock
421 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
423 mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
424 and r0, r0, #2 @ preserve bit P bit setting
425 orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
426 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
432 mrc p15, 1, r0, c0, c0, 1 @ get L2 present information
433 ands r0, r0, #0xf8
437 mrc p15, 0, r0, c1, c0, 0 @ get control register
438 bic r0, r0, r5 @ ..V. ..R. .... ..A.
439 orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)