Lines Matching refs:p15
44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
58 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
59 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
78 mcr p15, 0, ip, c7, c10, 4 @ drain WB
80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
82 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
85 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
110 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
112 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
114 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
129 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
149 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
150 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
151 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
167 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
168 mcr p15, 0, r0, c7, c10, 4 @ drain WB
177 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
178 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
180 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
184 mrc p15, 0, r0, c1, c0 @ get control register v4