Lines Matching refs:r0
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 bic r0, r0, #0x1800 @ ...iz...........
56 bic r0, r0, #0x0006 @ .............ca.
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 mov pc, r0
90 mov r0, #0
91 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
92 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
133 sub r3, r1, r0 @ calculate total size
137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
139 add r0, r0, #CACHE_DLINESIZE
140 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
142 add r0, r0, #CACHE_DLINESIZE
143 cmp r0, r1
175 bic r0, r0, #CACHE_DLINESIZE - 1
176 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
177 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
178 add r0, r0, #CACHE_DLINESIZE
179 cmp r0, r1
181 mcr p15, 0, r0, c7, c10, 4 @ drain WB
194 add r1, r0, r1
195 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
196 add r0, r0, #CACHE_DLINESIZE
197 cmp r0, r1
199 mov r0, #0
200 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
201 mcr p15, 0, r0, c7, c10, 4 @ drain WB
218 tst r0, #CACHE_DLINESIZE - 1
219 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
222 bic r0, r0, #CACHE_DLINESIZE - 1
223 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
224 add r0, r0, #CACHE_DLINESIZE
225 cmp r0, r1
227 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 bic r0, r0, #CACHE_DLINESIZE - 1
242 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 bic r0, r0, #CACHE_DLINESIZE - 1
260 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
261 add r0, r0, #CACHE_DLINESIZE
262 cmp r0, r1
264 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 add r1, r1, r0
303 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
304 add r0, r0, #CACHE_DLINESIZE
307 mcr p15, 0, r0, c7, c10, 4 @ drain WB
323 orr r0, r0, #0x18 @ cache the page table in L2
324 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
336 mov r0, r0
337 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
338 mcr p15, 0, r0, c7, c10, 4 @ drain WB
345 mov r0, #0
346 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
347 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
348 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
352 mov r0, #0 @ don't allow CP access
353 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
357 mrc p15, 0, r0, c1, c0 @ get control register
358 bic r0, r0, r5
359 orr r0, r0, r6