Lines Matching refs:r0
47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 * Params : r0 = address to jump to
67 mov pc, r0
74 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 sub r3, r1, r0 @ calculate total size
127 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
128 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
129 add r0, r0, #CACHE_DLINESIZE
130 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
131 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
132 add r0, r0, #CACHE_DLINESIZE
134 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
135 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
136 add r0, r0, #CACHE_DLINESIZE
137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
139 add r0, r0, #CACHE_DLINESIZE
141 cmp r0, r1
172 bic r0, r0, #CACHE_DLINESIZE - 1
173 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
174 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 cmp r0, r1
178 mcr p15, 0, r0, c7, c10, 4 @ drain WB
192 add r1, r0, r1
193 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
194 add r0, r0, #CACHE_DLINESIZE
195 cmp r0, r1
197 mov r0, #0
198 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
199 mcr p15, 0, r0, c7, c10, 4 @ drain WB
216 tst r0, #CACHE_DLINESIZE - 1
217 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
221 bic r0, r0, #CACHE_DLINESIZE - 1
222 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
223 add r0, r0, #CACHE_DLINESIZE
224 cmp r0, r1
226 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 bic r0, r0, #CACHE_DLINESIZE - 1
242 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
247 mcr p15, 0, r0, c7, c10, 4 @ drain WB
261 bic r0, r0, #CACHE_DLINESIZE - 1
264 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
266 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
268 add r0, r0, #CACHE_DLINESIZE
269 cmp r0, r1
271 mcr p15, 0, r0, c7, c10, 4 @ drain WB
281 add r1, r1, r0
312 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
313 add r0, r0, #CACHE_DLINESIZE
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
324 mov r0, #0
325 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
326 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
327 mcr p15, 0, r0, c7, c10, 4 @ drain WB
329 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
330 mcr p15, 0, r0, c6, c4, 0
331 mcr p15, 0, r0, c6, c5, 0
332 mcr p15, 0, r0, c6, c6, 0
333 mcr p15, 0, r0, c6, c7, 0
335 mov r0, #0x0000003F @ base = 0, size = 4GB
336 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
338 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
344 orr r0, r0, r2, lsl #1 @ the region register value
345 orr r0, r0, #1 @ set enable bit
346 mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
348 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
354 orr r0, r0, r2, lsl #1 @ the region register value
355 orr r0, r0, #1 @ set enable bit
356 mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
358 mov r0, #0x06
359 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
360 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
362 mov r0, #0x00 @ disable whole write buffer
364 mov r0, #0x02 @ region 1 write bufferred
366 mcr p15, 0, r0, c3, c0, 0
377 mov r0, #0x00000031
378 orr r0, r0, #0x00000200
379 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
380 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
382 mrc p15, 0, r0, c1, c0 @ get control register
383 orr r0, r0, #0x00001000 @ I-cache
384 orr r0, r0, #0x00000005 @ MPU/D-cache
386 orr r0, r0, #0x00004000 @ .1.. .... .... ....