Lines Matching refs:r0
40 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 bic r0, r0, #0x00001000 @ i-cache
42 bic r0, r0, #0x00000004 @ d-cache
43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
48 * Params : r0 = address to jump to
60 mov pc, r0
67 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
239 add r1, r1, r0
271 mov r0, #0
272 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
273 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
274 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
277 mcr p15, 0, r0, c6, c4, 0
278 mcr p15, 0, r0, c6, c5, 0
279 mcr p15, 0, r0, c6, c6, 0
280 mcr p15, 0, r0, c6, c7, 0
282 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
283 mcr p15, 0, r0, c6, c4, 1
284 mcr p15, 0, r0, c6, c5, 1
285 mcr p15, 0, r0, c6, c6, 1
286 mcr p15, 0, r0, c6, c7, 1
288 mov r0, #0x0000003F @ base = 0, size = 4GB
289 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
290 mcr p15, 0, r0, c6, c0, 1
292 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
298 orr r0, r0, r2, lsl #1 @ the area register value
299 orr r0, r0, #1 @ set enable bit
300 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
301 mcr p15, 0, r0, c6, c1, 1
303 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
309 orr r0, r0, r2, lsl #1 @ the area register value
310 orr r0, r0, #1 @ set enable bit
311 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
312 mcr p15, 0, r0, c6, c2, 1
314 mov r0, #0x06
315 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
316 mcr p15, 0, r0, c2, c0, 1
318 mov r0, #0x00 @ disable whole write buffer
320 mov r0, #0x02 @ Region 1 write bufferred
322 mcr p15, 0, r0, c3, c0, 0
324 mov r0, #0x10000
325 sub r0, r0, #1 @ r0 = 0xffff
326 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
327 mcr p15, 0, r0, c5, c0, 1
329 mrc p15, 0, r0, c1, c0 @ get control register
330 orr r0, r0, #0x00001000 @ I-cache
331 orr r0, r0, #0x00000005 @ MPU/D-cache