Lines Matching refs:c6
54 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
98 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
174 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
223 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
273 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
276 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
277 mcr p15, 0, r0, c6, c4, 0
278 mcr p15, 0, r0, c6, c5, 0
279 mcr p15, 0, r0, c6, c6, 0
280 mcr p15, 0, r0, c6, c7, 0
282 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
283 mcr p15, 0, r0, c6, c4, 1
284 mcr p15, 0, r0, c6, c5, 1
285 mcr p15, 0, r0, c6, c6, 1
286 mcr p15, 0, r0, c6, c7, 1
289 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
290 mcr p15, 0, r0, c6, c0, 1
300 mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
301 mcr p15, 0, r0, c6, c1, 1
311 mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
312 mcr p15, 0, r0, c6, c2, 1