• Home
  • History
  • Annotate
  • Raw
  • Download
  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/

Lines Matching refs:r0

74 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
75 bic r0, r0, #0x1000 @ ...i............
76 bic r0, r0, #0x000e @ ............wca.
77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
101 mov pc, r0
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
156 sub r3, r1, r0 @ calculate total size
160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
163 add r0, r0, #CACHE_DLINESIZE
164 cmp r0, r1
194 bic r0, r0, #CACHE_DLINESIZE - 1
195 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
197 add r0, r0, #CACHE_DLINESIZE
198 cmp r0, r1
200 mcr p15, 0, r0, c7, c10, 4 @ drain WB
213 add r1, r0, r1
214 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
215 add r0, r0, #CACHE_DLINESIZE
216 cmp r0, r1
218 mov r0, #0
219 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
237 tst r0, #CACHE_DLINESIZE - 1
238 bic r0, r0, #CACHE_DLINESIZE - 1
239 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
242 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
243 add r0, r0, #CACHE_DLINESIZE
244 cmp r0, r1
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
260 bic r0, r0, #CACHE_DLINESIZE - 1
261 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 add r0, r0, #CACHE_DLINESIZE
263 cmp r0, r1
265 mcr p15, 0, r0, c7, c10, 4 @ drain WB
277 bic r0, r0, #CACHE_DLINESIZE - 1
278 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
279 add r0, r0, #CACHE_DLINESIZE
280 cmp r0, r1
282 mcr p15, 0, r0, c7, c10, 4 @ drain WB
292 add r1, r1, r0
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 add r0, r0, #CACHE_DLINESIZE
362 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
376 mov r0, r0
377 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 mcr p15, 0, r0, c7, c10, 4 @ drain WB
386 mov r0, #0
387 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
388 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
390 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
394 mrc p15, 0, r0, c1, c0 @ get control register v4
395 bic r0, r0, r5
396 orr r0, r0, r6