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  • only in /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/

Lines Matching refs:r0

72 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
73 bic r0, r0, #0x1000 @ ...i............
74 bic r0, r0, #0x000e @ ............wca.
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mov pc, r0
106 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
154 sub r3, r1, r0 @ calculate total size
158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
161 add r0, r0, #CACHE_DLINESIZE
162 cmp r0, r1
192 bic r0, r0, #CACHE_DLINESIZE - 1
193 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 add r0, r0, #CACHE_DLINESIZE
196 cmp r0, r1
198 mcr p15, 0, r0, c7, c10, 4 @ drain WB
211 add r1, r0, r1
212 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 add r0, r0, #CACHE_DLINESIZE
214 cmp r0, r1
216 mov r0, #0
217 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
218 mcr p15, 0, r0, c7, c10, 4 @ drain WB
235 tst r0, #CACHE_DLINESIZE - 1
236 bic r0, r0, #CACHE_DLINESIZE - 1
237 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
240 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
241 add r0, r0, #CACHE_DLINESIZE
242 cmp r0, r1
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 bic r0, r0, #CACHE_DLINESIZE - 1
259 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
260 add r0, r0, #CACHE_DLINESIZE
261 cmp r0, r1
263 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
277 add r0, r0, #CACHE_DLINESIZE
278 cmp r0, r1
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 add r1, r1, r0
322 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
323 add r0, r0, #CACHE_DLINESIZE
358 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
372 mov r0, r0
373 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
374 mcr p15, 0, r0, c7, c10, 4 @ drain WB
382 mov r0, #0
383 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
384 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
386 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
390 mrc p15, 0, r0, c1, c0 @ get control register v4
391 bic r0, r0, r5
392 orr r0, r0, r6