Lines Matching refs:r0
39 mrc p15, 0, r0, c1, c0, 0
40 bic r0, r0, #0x3f000000 @ bank/f/lock/s
41 bic r0, r0, #0x0000000c @ w-buffer/cache
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
47 * Params : r0 = address to jump to
56 mov pc, r0
62 mov r0, #0
63 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
65 mcr p15, 0, r0, c6, c3 @ disable area 3~7
66 mcr p15, 0, r0, c6, c4
67 mcr p15, 0, r0, c6, c5
68 mcr p15, 0, r0, c6, c6
69 mcr p15, 0, r0, c6, c7
71 mov r0, #0x0000003F @ base = 0, size = 4GB
72 mcr p15, 0, r0, c6, c0 @ set area 0, default
74 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
80 orr r0, r0, r2, lsl #1 @ the area register value
81 orr r0, r0, #1 @ set enable bit
82 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
84 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
90 orr r0, r0, r2, lsl #1 @ the area register value
91 orr r0, r0, #1 @ set enable bit
92 mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
94 mov r0, #0x06
95 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
97 mov r0, #0x00 @ disable whole write buffer
99 mov r0, #0x02 @ Region 1 write bufferred
101 mcr p15, 0, r0, c3, c0
103 mov r0, #0x10000
104 sub r0, r0, #1 @ r0 = 0xffff
105 mcr p15, 0, r0, c5, c0 @ all read/write access
107 mrc p15, 0, r0, c1, c0 @ get control register
108 bic r0, r0, #0x3F000000 @ set to standard caching mode
110 orr r0, r0, #0x0000000d @ MPU/Cache/WB