Lines Matching refs:channels
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
49 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
50 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
56 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
62 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
68 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
74 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
80 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
86 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
87 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
88 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
92 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
93 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
98 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
99 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
104 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
105 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
110 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
111 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
116 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
117 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
122 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
126 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
130 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
134 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
141 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
152 .channels = {