Lines Matching refs:S3C24XX_GPIOREG2
22 #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
35 * S3C24XX_GPIOREG2 is for the second set of registers in the
39 #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
667 #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
736 #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
737 #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
738 #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
746 #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
747 #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
748 #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
749 #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
775 #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
776 #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
777 #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
778 #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
779 #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)