Lines Matching refs:channels
39 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
43 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
47 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
48 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
49 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
55 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
61 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
67 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
73 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
79 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
85 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
86 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
87 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
91 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
92 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
97 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
102 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
106 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
110 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
114 .channels[3] =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
121 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
132 .channels = {