Lines Matching refs:tmp_reg
108 u32 tmp_reg;
115 tmp_reg = __raw_readl(clk->parent_switch_reg);
117 if (!(tmp_reg & 1)) {
118 tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
119 __raw_writel(tmp_reg, clk->parent_switch_reg);
141 u32 tmp_reg;
148 tmp_reg = __raw_readl(clk->parent_switch_reg);
150 if (tmp_reg & 1) {
151 tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
152 __raw_writel(tmp_reg, clk->parent_switch_reg);
197 u32 tmp_reg, tmp_m, tmp_2p, i;
212 tmp_reg = __raw_readl(clk->scale_reg);
213 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
214 __raw_writel(tmp_reg, clk->scale_reg);
228 tmp_reg = __raw_readl(clk->scale_reg);
232 tmp_reg |= ((1 << 14) | (1 << 15));
233 __raw_writel(tmp_reg, clk->scale_reg);
248 tmp_reg |= ((i - 1) << 11);
250 tmp_reg |= (1 << 14); /*direct mode, no divide */
255 tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
256 tmp_reg |= (1 << 16); /*power up PLL */
257 __raw_writel(tmp_reg, clk->scale_reg);
263 tmp_reg = __raw_readl(clk->scale_reg);
264 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
265 __raw_writel(tmp_reg, clk->scale_reg);