Lines Matching refs:disable
191 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
206 /* set direct run for ARM or disable output for others */
209 /* disable source input as well (ignored for ARM) */
631 .disable = clk_reg_disable,
642 .disable = clk_reg_disable,
653 .disable = clk_reg_disable,
734 .disable = clk_reg_disable,
806 if (clk->disable)
807 clk->disable(clk);
966 if (clk->disable && !clk->usecount)
967 clk->disable(clk);
975 /* if ck_13MHz is not used, disable it. */