Lines Matching refs:UART1_REG
185 #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
195 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
203 buf[i] = readl(UART1_REG(RX));
215 while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
217 writel(buf[i++], UART1_REG(TX));
301 writel(0x83, UART1_REG(LCR));
302 writel(divisor & 0xff, UART1_REG(DLL));
303 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
304 writel(0x1b, UART1_REG(LCR));
305 writel(0x00, UART1_REG(IER));
306 writel(0x07, UART1_REG(FCR));
307 writel(0x00, UART1_REG(MCR));