Lines Matching refs:ORION5X_BRIDGE_VIRT_BASE
16 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100)
18 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104)
20 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108)
23 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
27 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110)
30 #define BRIDGE_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x114)
35 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200)
37 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204)
39 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300)