Lines Matching refs:serial_write_reg
164 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
180 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
181 serial_write_reg(p, UART_OMAP_SCR, 0x08);
182 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
183 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
194 serial_write_reg(p, UART_OMAP_MDR1, mdr1_val);
196 serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
224 serial_write_reg(p, UART_LCR, 0xBF);
227 serial_write_reg(p, UART_LCR, lcr);
232 serial_write_reg(p, UART_LCR, 0x80);
234 serial_write_reg(p, UART_LCR, lcr);
255 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
256 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
258 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
259 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
260 serial_write_reg(p, UART_IER, 0x0);
261 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
262 serial_write_reg(p, UART_DLL, uart->dll);
263 serial_write_reg(p, UART_DLM, uart->dlh);
264 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
265 serial_write_reg(p, UART_IER, uart->ier);
266 serial_write_reg(p, UART_LCR, 0x80);
267 serial_write_reg(p, UART_MCR, uart->mcr);
268 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
269 serial_write_reg(p, UART_EFR, efr);
270 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
271 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
272 serial_write_reg(p, UART_OMAP_WER, uart->wer);
273 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
277 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
354 serial_write_reg(p, UART_OMAP_SYSC, sysc);