Lines Matching defs:uart
176 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
178 struct plat_serial8250_port *p = uart->p;
188 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
191 struct plat_serial8250_port *p = uart->p;
207 dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n",
215 static void omap_uart_save_context(struct omap_uart_state *uart)
218 struct plat_serial8250_port *p = uart->p;
225 uart->dll = serial_read_reg(p, UART_DLL);
226 uart->dlh = serial_read_reg(p, UART_DLM);
228 uart->ier = serial_read_reg(p, UART_IER);
229 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
230 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
231 uart->wer = serial_read_reg(p, UART_OMAP_WER);
233 uart->mcr = serial_read_reg(p, UART_MCR);
236 uart->context_valid = 1;
239 static void omap_uart_restore_context(struct omap_uart_state *uart)
242 struct plat_serial8250_port *p = uart->p;
247 if (!uart->context_valid)
250 uart->context_valid = 0;
252 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
253 omap_uart_mdr1_errataset(uart, 0x07, 0xA0);
262 serial_write_reg(p, UART_DLL, uart->dll);
263 serial_write_reg(p, UART_DLM, uart->dlh);
265 serial_write_reg(p, UART_IER, uart->ier);
267 serial_write_reg(p, UART_MCR, uart->mcr);
271 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
272 serial_write_reg(p, UART_OMAP_WER, uart->wer);
273 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
274 if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
275 omap_uart_mdr1_errataset(uart, 0x00, 0xA1);
280 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
281 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
284 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
286 if (uart->clocked)
289 clk_enable(uart->ick);
290 clk_enable(uart->fck);
291 uart->clocked = 1;
292 omap_uart_restore_context(uart);
297 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
299 if (!uart->clocked)
302 omap_uart_save_context(uart);
303 uart->clocked = 0;
304 clk_disable(uart->ick);
305 clk_disable(uart->fck);
308 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
311 if (uart->wk_en && uart->wk_mask) {
312 u32 v = __raw_readl(uart->wk_en);
313 v |= uart->wk_mask;
314 __raw_writel(v, uart->wk_en);
318 if (cpu_is_omap34xx() && uart->padconf) {
319 u16 v = omap_ctrl_readw(uart->padconf);
321 omap_ctrl_writew(v, uart->padconf);
325 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
328 if (uart->wk_en && uart->wk_mask) {
329 u32 v = __raw_readl(uart->wk_en);
330 v &= ~uart->wk_mask;
331 __raw_writel(v, uart->wk_en);
335 if (cpu_is_omap34xx() && uart->padconf) {
336 u16 v = omap_ctrl_readw(uart->padconf);
338 omap_ctrl_writew(v, uart->padconf);
342 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
345 struct plat_serial8250_port *p = uart->p;
357 static void omap_uart_block_sleep(struct omap_uart_state *uart)
359 omap_uart_enable_clocks(uart);
361 omap_uart_smart_idle_enable(uart, 0);
362 uart->can_sleep = 0;
363 if (uart->timeout)
364 mod_timer(&uart->timer, jiffies + uart->timeout);
366 del_timer(&uart->timer);
369 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
371 if (device_may_wakeup(&uart->pdev.dev))
372 omap_uart_enable_wakeup(uart);
374 omap_uart_disable_wakeup(uart);
376 if (!uart->clocked)
379 omap_uart_smart_idle_enable(uart, 1);
380 uart->can_sleep = 1;
381 del_timer(&uart->timer);
386 struct omap_uart_state *uart = (struct omap_uart_state *)data;
388 omap_uart_allow_sleep(uart);
393 struct omap_uart_state *uart;
395 list_for_each_entry(uart, &uart_list, node) {
396 if (num == uart->num && uart->can_sleep) {
397 omap_uart_disable_clocks(uart);
405 struct omap_uart_state *uart;
407 list_for_each_entry(uart, &uart_list, node) {
408 if (num == uart->num) {
409 omap_uart_enable_clocks(uart);
412 if (cpu_is_omap34xx() && uart->padconf) {
413 u16 p = omap_ctrl_readw(uart->padconf);
416 omap_uart_block_sleep(uart);
420 if (__raw_readl(uart->wk_st) & uart->wk_mask)
421 omap_uart_block_sleep(uart);
429 struct omap_uart_state *uart;
431 list_for_each_entry(uart, &uart_list, node) {
432 omap_uart_allow_sleep(uart);
438 struct omap_uart_state *uart;
441 list_for_each_entry(uart, &uart_list, node) {
442 if (!uart->clocked)
445 if (!uart->can_sleep) {
451 omap_uart_allow_sleep(uart);
468 struct omap_uart_state *uart = dev_id;
470 omap_uart_block_sleep(uart);
475 static void omap_uart_idle_init(struct omap_uart_state *uart)
477 struct plat_serial8250_port *p = uart->p;
480 uart->can_sleep = 0;
481 uart->timeout = DEFAULT_TIMEOUT;
482 setup_timer(&uart->timer, omap_uart_idle_timer,
483 (unsigned long) uart);
484 if (uart->timeout)
485 mod_timer(&uart->timer, jiffies + uart->timeout);
486 omap_uart_smart_idle_enable(uart, 0);
489 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
493 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
494 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
495 switch (uart->num) {
509 uart->wk_mask = wk_mask;
510 uart->padconf = padconf;
515 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
516 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
518 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
519 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
521 switch (uart->num) {
532 uart->wk_mask = wk_mask;
534 uart->wk_en = NULL;
535 uart->wk_st = NULL;
536 uart->wk_mask = 0;
537 uart->padconf = 0;
542 "serial idle", (void *)uart);
549 struct omap_uart_state *uart;
551 list_for_each_entry(uart, &uart_list, node) {
553 ret = request_irq(uart->p->irq, omap_uart_interrupt,
554 IRQF_SHARED, "serial idle", (void *)uart);
556 free_irq(uart->p->irq, (void *)uart);
566 struct omap_uart_state *uart = container_of(pdev,
569 return sprintf(buf, "%u\n", uart->timeout / HZ);
578 struct omap_uart_state *uart = container_of(pdev,
587 uart->timeout = value * HZ;
588 if (uart->timeout)
589 mod_timer(&uart->timer, jiffies + uart->timeout);
592 omap_uart_block_sleep(uart);
601 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
693 struct omap_uart_state *uart = &omap_uart[i];
694 struct platform_device *pdev = &uart->pdev;
700 dev_warn(dev, "no physical address for uart#%d,"
710 dev_err(dev, "ioremap failed for uart%i\n", i + 1);
714 sprintf(name, "uart%d_ick", i + 1);
715 uart->ick = clk_get(NULL, name);
716 if (IS_ERR(uart->ick)) {
717 dev_err(dev, "Could not get uart%d_ick\n", i + 1);
718 uart->ick = NULL;
721 sprintf(name, "uart%d_fck", i+1);
722 uart->fck = clk_get(NULL, name);
723 if (IS_ERR(uart->fck)) {
724 dev_err(dev, "Could not get uart%d_fck\n", i + 1);
725 uart->fck = NULL;
729 if (!uart->ick || !uart->fck)
733 uart->num = i;
734 p->private_data = uart;
735 uart->p = p;
755 struct omap_uart_state *uart;
762 uart = &omap_uart[port];
763 pdev = &uart->pdev;
767 if (unlikely(!uart->ick || !uart->fck)) {
768 WARN(1, "%s: can't init uart%d, no clocks available\n",
773 omap_uart_enable_clocks(uart);
775 omap_uart_reset(uart);
776 omap_uart_idle_init(uart);
778 list_add_tail(&uart->node, &uart_list);
783 if ((cpu_is_omap34xx() && uart->padconf) ||
784 (uart->wk_en && uart->wk_mask)) {
795 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
796 else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
798 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
800 if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
801 uart->p->serial_in = serial_in_override;
802 uart->p->serial_out = serial_out_override;
807 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;