Lines Matching refs:new_div
221 * @new_div: ptr to where we should store the divisor
230 u32 *new_div)
243 *new_div = 1;
273 *new_div = clkr->div;
275 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
372 u32 new_div;
374 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
394 u32 field_val, validrate, new_div = 0;
399 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
403 field_val = _divisor_to_clksel(clk, new_div);
409 clk->rate = clk->parent->rate / new_div;