Lines Matching refs:actim_ctrla
166 u32 actim_ctrla = 0, actim_ctrlb = 0;
171 SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
172 SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
173 SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
174 SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
175 SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
176 SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
177 SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
178 SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
201 rx51_sdrc_params[id].actim_ctrla = actim_ctrla;