Lines Matching refs:MX51_GPC_BASE
19 #define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
488 #define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80)
489 #define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100)
490 #define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180)
491 #define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0)
492 #define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220)
493 #define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240)
494 #define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260)
495 #define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280)
496 #define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0)
497 #define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0)
498 #define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0)
499 #define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0)
500 #define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300)
533 #define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0)
534 #define MXC_GPC_PGR (MX51_GPC_BASE + 0x4)
535 #define MXC_GPC_VCR (MX51_GPC_BASE + 0x8)
536 #define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC)
537 #define MXC_GPC_NEON (MX51_GPC_BASE + 0x10)