Lines Matching refs:H2_PAD_CFG
586 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
589 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
591 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
592 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
593 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
594 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
595 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
596 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
597 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
598 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
599 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
600 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */