Lines Matching refs:CCM_CGR2
46 #define CCM_CGR2 0x34
391 DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
392 DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
393 DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
394 DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
395 DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
396 DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
397 DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
398 DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
399 DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
400 DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
401 DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
402 DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
403 DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
404 DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
405 DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
535 __raw_writel(cgr2, CCM_BASE + CCM_CGR2);