Lines Matching refs:clk_get_rate
117 return clk_get_rate(&ckih_clk);
145 return clk_get_rate(&ckih_clk);
207 return clk_get_rate(&serial_pll_clk);
209 return clk_get_rate(&mcu_pll_clk);
218 return clk_get_rate(clk->parent) / (max_pdf + 1);
227 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
236 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
245 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
256 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
270 return clk_get_rate(clk->parent) / (pre * post);
275 u32 pre, post, parent = clk_get_rate(clk->parent);
288 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
315 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
326 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
337 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
343 u32 parent = clk_get_rate(clk->parent);
357 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
378 return clk_get_rate(clk->parent) / 2;
387 return clk_get_rate(clk->parent) / (msti_pdf + 1);
396 return clk_get_rate(clk->parent) / (msti_pdf + 1);
608 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));