Lines Matching refs:CLKPWRBASE_REG
24 #define CLKPWRBASE_REG r6
46 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
49 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
68 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
70 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
71 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
83 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
87 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
90 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
93 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
96 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
100 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
109 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
118 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
122 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
128 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
129 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\