Lines Matching defs:enable_mask
35 u32 enable_mask;
56 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
63 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
70 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
91 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
97 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
112 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
119 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
127 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
135 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
143 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
148 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
153 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
158 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
163 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
168 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
173 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
178 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
183 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
188 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
193 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
198 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
248 v |= clk->enable_mask;
279 v &= ~clk->enable_mask;
339 div_bit = clk->enable_mask >> 15;