Lines Matching refs:ip
55 ldr ip, CACHE_FLUSH
56 blx ip
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
66 bic ip, ip, #DDR2_SRPD_BIT
67 orr ip, ip, #DDR2_LPMODEN_BIT
68 str ip, [r0, #DDR2_SDRCR_OFFSET]
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
71 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
72 str ip, [r0, #DDR2_SDRCR_OFFSET]
74 mov ip, #PHYRDY_CYCLES
75 1: subs ip, ip, #0x1
85 ldr ip, [r3, #PLLDIV1]
86 bic ip, ip, #PLLDIV_EN
87 str ip, [r3, #PLLDIV1]
90 ldr ip, [r3, #PLLCTL]
91 bic ip, ip, #PLLCTL_PLLENSRC
92 bic ip, ip, #PLLCTL_PLLEN
93 str ip, [r3, #PLLCTL]
96 mov ip, #PLL_BYPASS_CYCLES
97 2: subs ip, ip, #0x1
101 ldr ip, [r3, #PLLCTL]
102 orr ip, ip, #PLLCTL_PLLPWRDN
103 str ip, [r3, #PLLCTL]
106 ldr ip, [r4]
107 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
109 str ip, [r4]
114 ldr ip, [r4]
115 bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
116 str ip, [r4]
121 ldr ip, [r3, #PLLCTL]
122 bic ip, ip, #PLLCTL_PLLRST
123 str ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
127 bic ip, ip, #PLLCTL_PLLPWRDN
128 str ip, [r3, #PLLCTL]
130 mov ip, #PLL_RESET_CYCLES
131 3: subs ip, ip, #0x1
135 ldr ip, [r3, #PLLCTL]
136 orr ip, ip, #PLLCTL_PLLRST
137 str ip, [r3, #PLLCTL]
140 mov ip, #PLL_LOCK_CYCLES
141 4: subs ip, ip, #0x1
145 ldr ip, [r3, #PLLCTL]
146 bic ip, ip, #PLLCTL_PLLENSRC
147 orr ip, ip, #PLLCTL_PLLEN
148 str ip, [r3, #PLLCTL]
152 ldr ip, [r3, #PLLDIV1]
153 orr ip, ip, #PLLDIV_EN
154 str ip, [r3, #PLLDIV1]
166 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
167 bic ip, ip, #DDR2_MCLKSTOPEN_BIT
168 str ip, [r0, #DDR2_SDRCR_OFFSET]
170 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
171 bic ip, ip, #DDR2_LPMODEN_BIT
172 str ip, [r0, #DDR2_SDRCR_OFFSET]
190 ldr ip, [r1, r6]
191 bic ip, ip, #MDSTAT_STATE_MASK
192 orr ip, ip, r0
193 str ip, [r1, r6]
196 ldr ip, [r1, #PTCMD]
197 orr ip, ip, #0x1
198 str ip, [r1, #PTCMD]
202 ldr ip, [r1, #PTSTAT]
203 and ip, ip, #0x1
204 cmp ip, #0x0
211 ldr ip, [r1, r6]
212 and ip, ip, #MDSTAT_STATE_MASK
213 cmp ip, r0