Lines Matching refs:rate_hz
84 .rate_hz = AT91_SLOW_CLOCK,
299 rate = clk->rate_hz;
331 actual = clk->parent->rate_hz;
363 actual = clk->parent->rate_hz;
372 clk->rate_hz = actual;
403 clk->rate_hz = parent->rate_hz;
421 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
625 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
640 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
641 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
660 uhpck.rate_hz = utmi_clk.parent->rate_hz;
661 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
682 main_clk.rate_hz = main_clock;
685 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
687 if (plla.rate_hz > 300000000)
690 if (plla.rate_hz > 800000000)
693 if (plla.rate_hz > 209000000)
697 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
701 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
720 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
738 freq = mck.parent->rate_hz;
741 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
743 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
748 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
751 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
774 freq / 1000000, (unsigned) mck.rate_hz / 1000000,