Lines Matching refs:at91_set_A_periph
219 at91_set_A_periph(AT91_PIN_PA2, 0);
222 at91_set_A_periph(AT91_PIN_PA1, 1);
225 at91_set_A_periph(AT91_PIN_PA0, 1);
227 at91_set_A_periph(AT91_PIN_PA3, 1);
228 at91_set_A_periph(AT91_PIN_PA4, 1);
229 at91_set_A_periph(AT91_PIN_PA5, 1);
294 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
295 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
368 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
371 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
421 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
422 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
423 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
485 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
486 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
487 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
488 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
542 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
543 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
544 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
545 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
659 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
660 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
661 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
662 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
824 at91_set_A_periph(AT91_PIN_PC0, 1);
826 at91_set_A_periph(AT91_PIN_PC1, 1);
828 at91_set_A_periph(AT91_PIN_PA15, 1);
830 at91_set_A_periph(AT91_PIN_PA16, 1);
956 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
957 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
994 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
995 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
998 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
1000 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
1002 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
1004 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
1006 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
1008 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1045 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1046 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1088 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1089 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1092 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1094 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1131 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1132 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */