Lines Matching refs:at91_set_A_periph
179 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
181 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
182 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
183 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
184 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
185 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
186 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
188 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
191 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
284 at91_set_A_periph(AT91_PIN_PA12, 0);
288 at91_set_A_periph(AT91_PIN_PA16, 1);
291 at91_set_A_periph(AT91_PIN_PA17, 1);
293 at91_set_A_periph(AT91_PIN_PA18, 1);
294 at91_set_A_periph(AT91_PIN_PA19, 1);
295 at91_set_A_periph(AT91_PIN_PA20, 1);
299 at91_set_A_periph(AT91_PIN_PA1, 1);
302 at91_set_A_periph(AT91_PIN_PA0, 1);
304 at91_set_A_periph(AT91_PIN_PA3, 1);
305 at91_set_A_periph(AT91_PIN_PA4, 1);
306 at91_set_A_periph(AT91_PIN_PA5, 1);
315 at91_set_A_periph(AT91_PIN_PA6, 0);
319 at91_set_A_periph(AT91_PIN_PA21, 1);
322 at91_set_A_periph(AT91_PIN_PA22, 1);
324 at91_set_A_periph(AT91_PIN_PA23, 1);
325 at91_set_A_periph(AT91_PIN_PA24, 1);
326 at91_set_A_periph(AT91_PIN_PA25, 1);
330 at91_set_A_periph(AT91_PIN_PA7, 1);
333 at91_set_A_periph(AT91_PIN_PA8, 1);
335 at91_set_A_periph(AT91_PIN_PA9, 1);
336 at91_set_A_periph(AT91_PIN_PA10, 1);
337 at91_set_A_periph(AT91_PIN_PA11, 1);
411 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
417 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
444 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
445 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
446 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
447 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
580 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
583 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
693 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
694 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
695 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
744 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
745 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
746 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
747 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
787 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
788 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
835 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
836 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
837 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
839 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
840 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
841 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
842 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
843 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
844 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
845 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
846 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
847 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
849 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
850 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
851 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
852 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
853 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
855 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
856 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
894 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
895 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
896 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
897 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
898 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
899 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
900 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
901 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
902 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
903 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
904 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
1143 at91_set_A_periph(AT91_PIN_PB6, 1);
1145 at91_set_A_periph(AT91_PIN_PB7, 1);
1147 at91_set_A_periph(AT91_PIN_PB8, 1);
1149 at91_set_A_periph(AT91_PIN_PB9, 1);
1151 at91_set_A_periph(AT91_PIN_PB10, 1);
1153 at91_set_A_periph(AT91_PIN_PB11, 1);
1234 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1235 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1272 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1273 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
1276 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1278 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
1315 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1316 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1358 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1359 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */