Lines Matching refs:at91_set_A_periph
246 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
247 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
320 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
323 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
425 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
426 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
427 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
433 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
434 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
435 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
493 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
494 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
495 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
496 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
497 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
498 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
499 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
500 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
501 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
503 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
504 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
505 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
506 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
507 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
508 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
509 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
510 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
511 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
512 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
513 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
514 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
515 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
516 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
517 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
518 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
674 at91_set_A_periph(AT91_PIN_PB21, 1);
676 at91_set_A_periph(AT91_PIN_PB22, 1);
678 at91_set_A_periph(AT91_PIN_PB23, 1);
680 at91_set_A_periph(AT91_PIN_PB24, 1);
682 at91_set_A_periph(AT91_PIN_PB25, 1);
684 at91_set_A_periph(AT91_PIN_PB26, 1);
853 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
854 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
891 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
892 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
895 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
897 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
934 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
935 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
977 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
978 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */