Lines Matching refs:at91_set_A_periph
169 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
170 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
172 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
173 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
174 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
175 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
176 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
177 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
178 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
248 at91_set_A_periph(AT91_PIN_PA8, 0);
263 at91_set_A_periph(AT91_PIN_PA7, 1);
266 at91_set_A_periph(AT91_PIN_PA6, 1);
268 at91_set_A_periph(AT91_PIN_PA9, 1);
269 at91_set_A_periph(AT91_PIN_PA10, 1);
270 at91_set_A_periph(AT91_PIN_PA11, 1);
335 at91_set_A_periph(AT91_PIN_PA7, 1);
337 at91_set_A_periph(AT91_PIN_PA6, 1);
339 at91_set_A_periph(AT91_PIN_PA9, 1);
340 at91_set_A_periph(AT91_PIN_PA10, 1);
341 at91_set_A_periph(AT91_PIN_PA11, 1);
367 at91_set_A_periph(AT91_PIN_PA8, 0);
503 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
506 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
608 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
609 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
610 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
616 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
617 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
618 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
792 at91_set_A_periph(AT91_PIN_PB17, 1);
794 at91_set_A_periph(AT91_PIN_PB16, 1);
796 at91_set_A_periph(AT91_PIN_PB18, 1);
798 at91_set_A_periph(AT91_PIN_PB19, 1);
800 at91_set_A_periph(AT91_PIN_PB20, 1);
802 at91_set_A_periph(AT91_PIN_PB21, 1);
876 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
877 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
914 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
915 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
918 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
920 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
922 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
924 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
926 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
928 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
965 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
966 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
969 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
971 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
1008 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
1009 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
1012 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
1014 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
1051 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
1052 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
1132 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1133 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1271 at91_set_A_periph(AT91_PIN_PC8, 0);
1278 at91_set_A_periph(AT91_PIN_PC9, 0);
1308 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1309 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */