Lines Matching refs:at91_set_A_periph
168 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
169 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
170 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
171 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
172 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
173 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
174 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
175 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
176 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
177 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
268 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
269 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
270 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
271 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
274 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
333 at91_set_A_periph(AT91_PIN_PA27, 0);
348 at91_set_A_periph(AT91_PIN_PA28, 1);
351 at91_set_A_periph(AT91_PIN_PA29, 1);
425 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
426 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
498 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
501 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
550 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
551 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
552 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
562 at91_set_A_periph(cs_pin, 0);
737 at91_set_A_periph(AT91_PIN_PB0, 1);
739 at91_set_A_periph(AT91_PIN_PB1, 1);
741 at91_set_A_periph(AT91_PIN_PB2, 1);
743 at91_set_A_periph(AT91_PIN_PB3, 1);
745 at91_set_A_periph(AT91_PIN_PB4, 1);
747 at91_set_A_periph(AT91_PIN_PB5, 1);
779 at91_set_A_periph(AT91_PIN_PB6, 1);
781 at91_set_A_periph(AT91_PIN_PB7, 1);
783 at91_set_A_periph(AT91_PIN_PB8, 1);
785 at91_set_A_periph(AT91_PIN_PB9, 1);
787 at91_set_A_periph(AT91_PIN_PB10, 1);
789 at91_set_A_periph(AT91_PIN_PB11, 1);
821 at91_set_A_periph(AT91_PIN_PB12, 1);
823 at91_set_A_periph(AT91_PIN_PB13, 1);
825 at91_set_A_periph(AT91_PIN_PB14, 1);
827 at91_set_A_periph(AT91_PIN_PB15, 1);
829 at91_set_A_periph(AT91_PIN_PB16, 1);
831 at91_set_A_periph(AT91_PIN_PB17, 1);
916 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
917 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
954 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
955 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
958 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
1003 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1004 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1007 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1009 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1011 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1013 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1015 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1017 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1054 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1055 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */